1983     hevc_vepu580_control_cfg *reg_ctl = &regs->reg_ctl;  in vepu580_h265_set_pp_regs()  local
1988     reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;  in vepu580_h265_set_pp_regs()
2171     cfg.reg = (RK_U32*)&hw_regs->reg_ctl;  in hal_h265e_v580_send_regs()
2182         regs = (RK_U32*)&hw_regs->reg_ctl;  in hal_h265e_v580_send_regs()
2574     hevc_vepu580_control_cfg *reg_ctl = &regs->reg_ctl;  in vepu580_h265e_use_pass1_patch()  local
2582     reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;  in vepu580_h265e_use_pass1_patch()
2639         regs->reg_ctl.reg0008_int_en.slc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo;  in vepu580_setup_split()
2663             regs->reg_ctl.reg0008_int_en.slc_done_en = 1 ;  in vepu580_setup_split()
2685     hevc_vepu580_control_cfg *reg_ctl = &regs->reg_ctl;  in hal_h265e_v580_gen_regs()  local
2704     reg_ctl->reg0004_enc_strt.lkt_num      = 0;  in hal_h265e_v580_gen_regs()
2705     reg_ctl->reg0004_enc_strt.vepu_cmd     = ctx->enc_mode;  in hal_h265e_v580_gen_regs()
2706     reg_ctl->reg0005_enc_clr.safe_clr      = 0x0;  in hal_h265e_v580_gen_regs()
2707     reg_ctl->reg0005_enc_clr.force_clr     = 0x0;  in hal_h265e_v580_gen_regs()
2709     reg_ctl->reg0008_int_en.enc_done_en         = 1;  in hal_h265e_v580_gen_regs()
2710     reg_ctl->reg0008_int_en.lkt_node_done_en    = 1;  in hal_h265e_v580_gen_regs()
2711     reg_ctl->reg0008_int_en.sclr_done_en        = 1;  in hal_h265e_v580_gen_regs()
2712     reg_ctl->reg0008_int_en.slc_done_en         = 0;  in hal_h265e_v580_gen_regs()
2713     reg_ctl->reg0008_int_en.bsf_oflw_en         = 1;  in hal_h265e_v580_gen_regs()
2714     reg_ctl->reg0008_int_en.brsp_otsd_en        = 1;  in hal_h265e_v580_gen_regs()
2715     reg_ctl->reg0008_int_en.wbus_err_en         = 1;  in hal_h265e_v580_gen_regs()
2716     reg_ctl->reg0008_int_en.rbus_err_en         = 1;  in hal_h265e_v580_gen_regs()
2717     reg_ctl->reg0008_int_en.wdg_en              = 1;  in hal_h265e_v580_gen_regs()
2718     reg_ctl->reg0008_int_en.lkt_err_int_en      = 0;  in hal_h265e_v580_gen_regs()
2720     reg_ctl->reg0012_dtrns_map.lpfw_bus_ordr    = 0x0;  in hal_h265e_v580_gen_regs()
2721     reg_ctl->reg0012_dtrns_map.cmvw_bus_ordr    = 0x0;  in hal_h265e_v580_gen_regs()
2722     reg_ctl->reg0012_dtrns_map.dspw_bus_ordr    = 0x0;  in hal_h265e_v580_gen_regs()
2723     reg_ctl->reg0012_dtrns_map.rfpw_bus_ordr    = 0x0;  in hal_h265e_v580_gen_regs()
2724     reg_ctl->reg0012_dtrns_map.src_bus_edin     = 0x0;  in hal_h265e_v580_gen_regs()
2725     reg_ctl->reg0012_dtrns_map.meiw_bus_edin    = 0x0;  in hal_h265e_v580_gen_regs()
2726     reg_ctl->reg0012_dtrns_map.bsw_bus_edin     = 0x7;  in hal_h265e_v580_gen_regs()
2727     reg_ctl->reg0012_dtrns_map.lktr_bus_edin    = 0x0;  in hal_h265e_v580_gen_regs()
2728     reg_ctl->reg0012_dtrns_map.roir_bus_edin    = 0x0;  in hal_h265e_v580_gen_regs()
2729     reg_ctl->reg0012_dtrns_map.lktw_bus_edin    = 0x0;  in hal_h265e_v580_gen_regs()
2730     reg_ctl->reg0012_dtrns_map.afbc_bsize       = 0x1;  in hal_h265e_v580_gen_regs()
2731     reg_ctl->reg0012_dtrns_map.ebufw_bus_ordr   = 0x0;  in hal_h265e_v580_gen_regs()
2733     reg_ctl->reg0013_dtrns_cfg.dspr_otsd        = (ctx->frame_type == INTER_P_FRAME);  in hal_h265e_v580_gen_regs()
2734     reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke     = 0x0;  in hal_h265e_v580_gen_regs()
2735     reg_ctl->reg0014_enc_wdg.vs_load_thd        = 0x1fffff;  in hal_h265e_v580_gen_regs()
2736     reg_ctl->reg0014_enc_wdg.rfp_load_thd       = 0;  in hal_h265e_v580_gen_regs()
2738     reg_ctl->reg0021_func_en.cke                = 1;  in hal_h265e_v580_gen_regs()
2739     reg_ctl->reg0021_func_en.resetn_hw_en       = 1;  in hal_h265e_v580_gen_regs()
2740     reg_ctl->reg0021_func_en.enc_done_tmvp_en   = 1;  in hal_h265e_v580_gen_regs()