rkenc/h265e/hal_h265e_vepu580.c

135     H265eV580RegSet     *regs_set[MAX_TILE_NUM];
1332 static void vepu580_h265_global_cfg_set(H265eV580HalContext *ctx, H265eV580RegSet *regs)  in vepu580_h265_global_cfg_set()
1539         frm_cfg->regs_set[0] = mpp_calloc(H265eV580RegSet, 1);  in hal_h265e_v580_init()
1759     H265eV580RegSet *regs = frm->regs_set[0];  in setup_intra_refresh()
1890 static MPP_RET vepu580_h265_set_rc_regs(H265eV580HalContext *ctx, H265eV580RegSet *regs, HalEncTask…  in vepu580_h265_set_rc_regs()
1980 static MPP_RET vepu580_h265_set_pp_regs(H265eV580RegSet *regs, VepuFmtCfg *fmt,  in vepu580_h265_set_pp_regs()
2163 static MPP_RET hal_h265e_v580_send_regs(MppDev dev, H265eV580RegSet *hw_regs, H265eV580StatusElem *…  in hal_h265e_v580_send_regs()
2290     H265eV580RegSet *regs = frm->regs_set[0];  in setup_vepu580_dual_core()
2536 static MPP_RET vepu580_h265e_save_pass1_patch(H265eV580RegSet *regs, H265eV580HalContext *ctx,  in vepu580_h265e_save_pass1_patch()
2571 static MPP_RET vepu580_h265e_use_pass1_patch(H265eV580RegSet *regs, H265eV580HalContext *ctx)  in vepu580_h265e_use_pass1_patch()
2611 static void vepu580_setup_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)  in vepu580_setup_split()
2681     H265eV580RegSet *regs = frm_cfg->regs_set[0];  in hal_h265e_v580_gen_regs()
2699     memset(regs, 0, sizeof(H265eV580RegSet));  in hal_h265e_v580_gen_regs()
2885         H265eV580RegSet *hw_regs = frm->regs_set[k];  in hal_h265e_v580_start()
2890             hw_regs = mpp_malloc(H265eV580RegSet, 1);  in hal_h265e_v580_start()
3210         H265eV580RegSet *regs = frm->regs_set[0];  in hal_h265e_v580_wait()
3274         H265eV580RegSet *regs = frm->regs_set[0];  in hal_h265e_v580_wait()