428     hevc_vepu540c_wgt *reg_wgt = &regs->reg_wgt;  in vepu540c_h265_global_cfg_set()  local
437         reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 11;  in vepu540c_h265_global_cfg_set()
438         memcpy(&reg_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_moda_qp, sizeof(lamd_moda_qp));  in vepu540c_h265_global_cfg_set()
444         reg_wgt->iprd_lamb_satd_ofst.lambda_satd_offset = 11;  in vepu540c_h265_global_cfg_set()
445         memcpy(&reg_wgt->rdo_wgta_qp_grpa_0_51[0], lamd_modb_qp, sizeof(lamd_modb_qp));  in vepu540c_h265_global_cfg_set()
447     reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;  in vepu540c_h265_global_cfg_set()
448     reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;  in vepu540c_h265_global_cfg_set()
450         reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i;  in vepu540c_h265_global_cfg_set()
451         reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p;  in vepu540c_h265_global_cfg_set()
456         regs->reg_wgt.me_sqi_cfg.cime_pmv_num = 1;  in vepu540c_h265_global_cfg_set()
457         regs->reg_wgt.me_sqi_cfg.cime_fuse   = 1;  in vepu540c_h265_global_cfg_set()
458         regs->reg_wgt.me_sqi_cfg.itp_mode    = 0;  in vepu540c_h265_global_cfg_set()
459         regs->reg_wgt.me_sqi_cfg.move_lambda = 2;  in vepu540c_h265_global_cfg_set()
460         regs->reg_wgt.me_sqi_cfg.rime_lvl_mrg     = 0;  in vepu540c_h265_global_cfg_set()
461         regs->reg_wgt.me_sqi_cfg.rime_prelvl_en   = 3;  in vepu540c_h265_global_cfg_set()
462         regs->reg_wgt.me_sqi_cfg.rime_prersu_en   = 3;  in vepu540c_h265_global_cfg_set()
465         regs->reg_wgt.cime_mvd_th.cime_mvd_th0 = 8;  in vepu540c_h265_global_cfg_set()
466         regs->reg_wgt.cime_mvd_th.cime_mvd_th1 = 20;  in vepu540c_h265_global_cfg_set()
467         regs->reg_wgt.cime_mvd_th.cime_mvd_th2 = 32;  in vepu540c_h265_global_cfg_set()
470         regs->reg_wgt.cime_madp_th.cime_madp_th = 16;  in vepu540c_h265_global_cfg_set()
473         regs->reg_wgt.cime_multi.cime_multi0 = 8;  in vepu540c_h265_global_cfg_set()
474         regs->reg_wgt.cime_multi.cime_multi1 = 12;  in vepu540c_h265_global_cfg_set()
475         regs->reg_wgt.cime_multi.cime_multi2 = 16;  in vepu540c_h265_global_cfg_set()
476         regs->reg_wgt.cime_multi.cime_multi3 = 20;  in vepu540c_h265_global_cfg_set()
482         regs->reg_wgt.rime_mvd_th.rime_mvd_th0  = 1;  in vepu540c_h265_global_cfg_set()
483         regs->reg_wgt.rime_mvd_th.rime_mvd_th1  = 2;  in vepu540c_h265_global_cfg_set()
484         regs->reg_wgt.rime_mvd_th.fme_madp_th   = 0;  in vepu540c_h265_global_cfg_set()
487         regs->reg_wgt.rime_madp_th.rime_madp_th0 = 8;  in vepu540c_h265_global_cfg_set()
488         regs->reg_wgt.rime_madp_th.rime_madp_th1 = 16;  in vepu540c_h265_global_cfg_set()
491         regs->reg_wgt.rime_multi.rime_multi0 = 4;  in vepu540c_h265_global_cfg_set()
492         regs->reg_wgt.rime_multi.rime_multi1 = 8;  in vepu540c_h265_global_cfg_set()
493         regs->reg_wgt.rime_multi.rime_multi2 = 12;  in vepu540c_h265_global_cfg_set()
496         regs->reg_wgt.cmv_st_th.cmv_th0 = 64;  in vepu540c_h265_global_cfg_set()
497         regs->reg_wgt.cmv_st_th.cmv_th1 = 96;  in vepu540c_h265_global_cfg_set()
498         regs->reg_wgt.cmv_st_th.cmv_th2 = 128;  in vepu540c_h265_global_cfg_set()
1397     cfg.reg =  &hw_regs->reg_wgt;  in hal_h265e_v540c_start()
1408         regs = (RK_U32*)&hw_regs->reg_wgt;  in hal_h265e_v540c_start()