130     MppEncPrepCfg *prep = &ctx->cfg->prep;  in vepu540c_h265_setup_hal_bufs()  local
134     RK_S32 aligned_w = MPP_ALIGN(prep->width,  alignment);  in vepu540c_h265_setup_hal_bufs()
138     mb_wd64 = (prep->width + 63) / 64;  in vepu540c_h265_setup_hal_bufs()
139     mb_h64 = (prep->height + 63) / 64;  in vepu540c_h265_setup_hal_bufs()
141     frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);  in vepu540c_h265_setup_hal_bufs()
142     vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);  in vepu540c_h265_setup_hal_bufs()
589     MppEncPrepCfg *prep = &ctx->cfg->prep;  in hal_h265e_vepu540c_prepare()  local
593     if (prep->change_res) {  in hal_h265e_vepu540c_prepare()
601         prep->change_res = 0;  in hal_h265e_vepu540c_prepare()
1161         RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64;  in vepu540c_h265_set_split()
1162         RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 64) / 64;  in vepu540c_h265_set_split()
1304     vepu540c_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep);  in hal_h265e_v540c_gen_regs()
1315                          ctx->cfg->prep.width, ctx->cfg->prep.height);  in hal_h265e_v540c_gen_regs()
1457     RK_S32 mb64_num = ((cfg->prep.width + 63) / 64) * ((cfg->prep.height + 63) / 64);  in vepu540c_h265_set_feedback()