1711     reg_frm->common.sli_splt.sli_splt = 0;  in vepu510_h265e_save_pass1_patch()
1823         regs->reg_frm.common.sli_splt.sli_splt = 0;  in setup_vepu510_split()
1824         regs->reg_frm.common.sli_splt.sli_splt_mode = 0;  in setup_vepu510_split()
1825         regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;  in setup_vepu510_split()
1826         regs->reg_frm.common.sli_splt.sli_max_num_m1 = 0;  in setup_vepu510_split()
1827         regs->reg_frm.common.sli_splt.sli_flsh = 0;  in setup_vepu510_split()
1834         regs->reg_frm.common.sli_splt.sli_splt = 1;  in setup_vepu510_split()
1835         regs->reg_frm.common.sli_splt.sli_splt_mode = 0;  in setup_vepu510_split()
1836         regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;  in setup_vepu510_split()
1837         regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;  in setup_vepu510_split()
1838         regs->reg_frm.common.sli_splt.sli_flsh = 1;  in setup_vepu510_split()
1855         regs->reg_frm.common.sli_splt.sli_splt = 1;  in setup_vepu510_split()
1856         regs->reg_frm.common.sli_splt.sli_splt_mode = 1;  in setup_vepu510_split()
1857         regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;  in setup_vepu510_split()
1858         regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;  in setup_vepu510_split()
1859         regs->reg_frm.common.sli_splt.sli_flsh = 1;  in setup_vepu510_split()