306     MppEncPrepCfg *prep = &ctx->cfg->prep;  in vepu510_h265_setup_hal_bufs()  local
310     RK_S32 aligned_w = MPP_ALIGN(prep->width,  alignment);  in vepu510_h265_setup_hal_bufs()
314     mb_wd64 = (prep->width + 63) / 64;  in vepu510_h265_setup_hal_bufs()
315     mb_h64 = (prep->height + 63) / 64 + 1;  in vepu510_h265_setup_hal_bufs()
317     frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);  in vepu510_h265_setup_hal_bufs()
318     vepu5xx_set_fmt(fmt, ctx->cfg->prep.format);  in vepu510_h265_setup_hal_bufs()
380         RK_S32 ctu_w = (prep->width + 31) / 32;  in vepu510_h265_setup_hal_bufs()
381         RK_S32 ctu_h = (prep->height + 31) / 32;  in vepu510_h265_setup_hal_bufs()
1185     MppEncPrepCfg *prep = &ctx->cfg->prep;  in hal_h265e_vepu510_prepare()  local
1189     if (prep->change_res) {  in hal_h265e_vepu510_prepare()
1197         prep->change_res = 0;  in hal_h265e_vepu510_prepare()
1687     RK_S32 width = ctx->cfg->prep.width;  in vepu510_h265e_save_pass1_patch()
1688     RK_S32 height = ctx->cfg->prep.height;  in vepu510_h265e_save_pass1_patch()
1721     RK_U32 hor_stride = MPP_ALIGN(ctx->cfg->prep.width, 16);  in vepu510_h265e_use_pass1_patch()
1846         RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 32) / 32;  in setup_vepu510_split()
1847         RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 32) / 32;  in setup_vepu510_split()
2045     vepu510_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep);  in hal_h265e_v510_gen_regs()
2058                         ctx->cfg->prep.width, ctx->cfg->prep.height);  in hal_h265e_v510_gen_regs()
2227     RK_S32 mb8_num = MPP_ALIGN(cfg->prep.width, 8) * MPP_ALIGN(cfg->prep.height, 8) / 64;  in vepu510_h265_set_feedback()