1315         reg_frm->common.enc_pic.pic_qp    = rc_cfg->quality_target;  in vepu510_h265_set_rc_regs()
1327         reg_frm->common.enc_pic.pic_qp      = rc_cfg->quality_target;  in vepu510_h265_set_rc_regs()
1357                 reg_frm->common.enc_pic.pic_qp = fqp_min;  in vepu510_h265_set_rc_regs()
1537     regs->common.enc_pic.num_pic_tot_cur_hevc   = syn->sp.tot_poc_num;  in vepu510_h265_set_slice_regs()
1654         regs->common.enc_pic.mei_stor = 1;  in vepu510_h265_set_hw_address()
1657         regs->common.enc_pic.mei_stor = 0;  in vepu510_h265_set_hw_address()
1700     reg_frm->common.enc_pic.cur_frm_ref = 1;  in vepu510_h265e_save_pass1_patch()
1703     reg_frm->common.enc_pic.rec_fbc_dis = 1;  in vepu510_h265e_save_pass1_patch()
1712     reg_frm->common.enc_pic.slen_fifo = 0;  in vepu510_h265e_save_pass1_patch()
1831         regs->reg_frm.common.enc_pic.slen_fifo = 0;  in setup_vepu510_split()
1842         regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;  in setup_vepu510_split()
1843         regs->reg_ctl.int_en.vslc_done_en = regs->reg_frm.common.enc_pic.slen_fifo ;  in setup_vepu510_split()
1863         regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;  in setup_vepu510_split()
1865             (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN)))  in setup_vepu510_split()
2003     reg_frm->common.enc_pic.enc_stnd            = 1; //H265  in hal_h265e_v510_gen_regs()
2004 …reg_frm->common.enc_pic.cur_frm_ref         = !syn->sp.non_reference_flag; //current frame will be…  in hal_h265e_v510_gen_regs()
2005     reg_frm->common.enc_pic.bs_scp              = 1;  in hal_h265e_v510_gen_regs()
2006     reg_frm->common.enc_pic.log2_ctu_num_hevc   = mpp_ceil_log2(pic_wd32 * pic_h32);  in hal_h265e_v510_gen_regs()