117 static MPP_RET vdpu384a_setup_scale_origin_bufs(H264dHalCtx_t *p_hal, MppFrame mframe)  in vdpu384a_setup_scale_origin_bufs()  argument
119     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_setup_scale_origin_bufs()
143 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)  in prepare_spspps()  argument
147     DXVA_PicParams_H264_MVC *pp = p_hal->pp;  in prepare_spspps()
153     if (!p_hal->fast_mode && !pp->spspps_update) {  in prepare_spspps()
276                 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;  in prepare_spspps()
277                 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;  in prepare_spspps()
278                 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;  in prepare_spspps()
302 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)  in prepare_scanlist()  argument
306     if (!p_hal->pp->scaleing_list_enable_flag)  in prepare_scanlist()
312             data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 0];  in prepare_scanlist()
313             data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 1];  in prepare_scanlist()
314             data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 2];  in prepare_scanlist()
315             data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 3];  in prepare_scanlist()
328                     data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 0];  in prepare_scanlist()
329                     data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 1];  in prepare_scanlist()
330                     data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 2];  in prepare_scanlist()
331                     data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 3];  in prepare_scanlist()
351 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu384aH264dRegSet *regs, HalTaskInfo *task)  in set_registers()  argument
353     DXVA_PicParams_H264_MVC *pp = p_hal->pp;  in set_registers()
356     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in set_registers()
359     regs->h264d_paras.reg66_stream_len = p_hal->strm_len;  in set_registers()
369         mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);  in set_registers()
414         mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);  in set_registers()
423         mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);  in set_registers()
445             mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);  in set_registers()
446             mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);  in set_registers()
462             mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);  in set_registers()
472         mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);  in set_registers()
480         mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);  in set_registers()
486         mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);  in set_registers()
490         mpp_dev_set_reg_offset(p_hal->dev, 130, mpp_buffer_get_size(mbuffer));  in set_registers()
498                               8 * p_hal->strm_len, 128, 0);  in set_registers()
510         mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);  in set_registers()
511         mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits,  in set_registers()
526 …        vdpu384a_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);  in set_registers()
530 …        vdpu384a_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);  in set_registers()
590     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_init()  local
592     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_init()
595     MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu384aH264dRegCtx)));  in vdpu384a_h264d_init()
596     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_init()
597     RK_U32 max_cnt = p_hal->fast_mode ? VDPU384A_FAST_REG_SET_CNT : 1;  in vdpu384a_h264d_init()
601     FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs,  in vdpu384a_h264d_init()
613     mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);  in vdpu384a_h264d_init()
615     if (!p_hal->fast_mode) {  in vdpu384a_h264d_init()
621     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);  in vdpu384a_h264d_init()
622     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);  in vdpu384a_h264d_init()
623     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);  in vdpu384a_h264d_init()
640     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_deinit()  local
641     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_deinit()
644     RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;  in vdpu384a_h264d_deinit()
654     loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;  in vdpu384a_h264d_deinit()
662     if (p_hal->cmv_bufs) {  in vdpu384a_h264d_deinit()
663         hal_bufs_deinit(p_hal->cmv_bufs);  in vdpu384a_h264d_deinit()
664         p_hal->cmv_bufs = NULL;  in vdpu384a_h264d_deinit()
672     MPP_FREE(p_hal->reg_ctx);  in vdpu384a_h264d_deinit()
677 static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu384aRcbInfo *rcb_info,  in h264d_refine_rcb_size()  argument
681     RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;  in h264d_refine_rcb_size()
682     RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;  in h264d_refine_rcb_size()
683     RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;  in h264d_refine_rcb_size()
727     H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal;  in hal_h264d_rcb_info_update()  local
728     RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;  in hal_h264d_rcb_info_update()
729     RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;  in hal_h264d_rcb_info_update()
730     RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;  in hal_h264d_rcb_info_update()
731     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in hal_h264d_rcb_info_update()
732     RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);  in hal_h264d_rcb_info_update()
733     RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);  in hal_h264d_rcb_info_update()
741         RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1;  in hal_h264d_rcb_info_update()
753             mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);  in hal_h264d_rcb_info_update()
767     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_gen_regs()  local
768     RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);  in vdpu384a_h264d_gen_regs()
769     RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);  in vdpu384a_h264d_gen_regs()
770     Vdpu384aH264dRegCtx *ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_gen_regs()
775     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_gen_regs()
778         (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {  in vdpu384a_h264d_gen_regs()
783     if (!p_hal->pp->frame_mbs_only_flag)  in vdpu384a_h264d_gen_regs()
786     if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {  in vdpu384a_h264d_gen_regs()
789         if (p_hal->cmv_bufs) {  in vdpu384a_h264d_gen_regs()
790             hal_bufs_deinit(p_hal->cmv_bufs);  in vdpu384a_h264d_gen_regs()
791             p_hal->cmv_bufs = NULL;  in vdpu384a_h264d_gen_regs()
794         hal_bufs_init(&p_hal->cmv_bufs);  in vdpu384a_h264d_gen_regs()
795         if (p_hal->cmv_bufs == NULL) {  in vdpu384a_h264d_gen_regs()
799         p_hal->mv_size = mv_size;  in vdpu384a_h264d_gen_regs()
800         p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);  in vdpu384a_h264d_gen_regs()
801         hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);  in vdpu384a_h264d_gen_regs()
804 … mpp_buf_slot_get_prop(p_hal->frame_slots, p_hal->pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);  in vdpu384a_h264d_gen_regs()
807         vdpu384a_setup_scale_origin_bufs(p_hal, mframe);  in vdpu384a_h264d_gen_regs()
810     if (p_hal->fast_mode) {  in vdpu384a_h264d_gen_regs()
837     prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps) / 8);  in vdpu384a_h264d_gen_regs()
838     prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));  in vdpu384a_h264d_gen_regs()
839     set_registers(p_hal, regs, task);  in vdpu384a_h264d_gen_regs()
846     mpp_dev_set_reg_offset(p_hal->dev, 131, ctx->spspps_offset);  in vdpu384a_h264d_gen_regs()
848     if (p_hal->pp->scaleing_list_enable_flag) {  in vdpu384a_h264d_gen_regs()
851         mpp_dev_set_reg_offset(p_hal->dev, 132, ctx->sclst_offset);  in vdpu384a_h264d_gen_regs()
856     hal_h264d_rcb_info_update(p_hal);  in vdpu384a_h264d_gen_regs()
857     vdpu384a_setup_rcb(&regs->common_addr, p_hal->dev, p_hal->fast_mode ?  in vdpu384a_h264d_gen_regs()
870     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_start()  local
871     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_start()
874         (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {  in vdpu384a_h264d_start()
878     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_start()
879     Vdpu384aH264dRegSet *regs = p_hal->fast_mode ?  in vdpu384a_h264d_start()
882     MppDev dev = p_hal->dev;  in vdpu384a_h264d_start()
951     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_wait()  local
953     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_wait()
954     Vdpu384aH264dRegCtx *reg_ctx = (Vdpu384aH264dRegCtx *)p_hal->reg_ctx;  in vdpu384a_h264d_wait()
955     Vdpu384aH264dRegSet *p_regs = p_hal->fast_mode ?  in vdpu384a_h264d_wait()
960         (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {  in vdpu384a_h264d_wait()
964     ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);  in vdpu384a_h264d_wait()
969     if (p_hal->dec_cb) {  in vdpu384a_h264d_wait()
986         mpp_callback(p_hal->dec_cb, &param);  in vdpu384a_h264d_wait()
989     if (p_hal->fast_mode) {  in vdpu384a_h264d_wait()
1001     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_reset()  local
1003     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_reset()
1013     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_flush()  local
1015     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_flush()
1024     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;  in vdpu384a_h264d_control()  local
1026     INP_CHECK(ret, NULL == p_hal);  in vdpu384a_h264d_control()
1036             mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);  in vdpu384a_h264d_control()
1039             vdpu384a_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);  in vdpu384a_h264d_control()
1041             mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);  in vdpu384a_h264d_control()