Lines Matching refs:p_reg
43 static MPP_RET set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg) in set_device_regs() argument
47 p_reg->sw53.dec_fmt_sel = 0; //!< set H264 mode in set_device_regs()
48 p_reg->sw54.dec_out_endian = 1; //!< little endian in set_device_regs()
49 p_reg->sw54.dec_in_endian = 0; //!< big endian in set_device_regs()
50 p_reg->sw54.dec_strendian_e = 1; //!< little endian in set_device_regs()
51 p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled in set_device_regs()
52 p_reg->sw56.dec_max_burlen = 16; //!< (0, 4, 8, 16) choice one in set_device_regs()
53 p_reg->sw50.dec_ascmd0_dis = 0; //!< disable in set_device_regs()
54 p_reg->sw50.adv_pref_dis = 0; //!< disable in set_device_regs()
55 p_reg->sw52.adv_pref_thrd = 8; in set_device_regs()
56 p_reg->sw50.adtion_latency = 0; //!< compensation for bus latency; values up to 63 in set_device_regs()
57 p_reg->sw56.dec_data_discd_en = 0; in set_device_regs()
58 p_reg->sw54.dec_out_wordsp = 1;//!< little endian in set_device_regs()
59 p_reg->sw54.dec_in_wordsp = 1;//!< little endian in set_device_regs()
60 p_reg->sw54.dec_strm_wordsp = 1;//!< little endian in set_device_regs()
61 p_reg->sw57.timeout_sts_en = 1; in set_device_regs()
62 p_reg->sw57.dec_clkgate_en = 1; in set_device_regs()
63 p_reg->sw55.dec_irq_dis = 0; in set_device_regs()
65 p_reg->sw56.dec_axi_id_rd = (0xFF & 0xFFU); //!< 0-255 in set_device_regs()
66 p_reg->sw56.dec_axi_id_wr = (0x0 & 0xFFU); //!< 0-255 in set_device_regs()
70 p_reg->sw59.pflt_set0_tap0 = 1; in set_device_regs()
72 p_reg->sw59.pflt_set0_tap1 = val; in set_device_regs()
73 p_reg->sw59.pflt_set0_tap2 = 20; in set_device_regs()
75 p_reg->sw50.adtion_latency = 0; in set_device_regs()
77 p_reg->sw57.dec_clkgate_en = 1; in set_device_regs()
78 p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled in set_device_regs()
80 p_reg->sw56.dec_max_burlen = 16; in set_device_regs()
81 p_reg->sw56.dec_data_discd_en = 0; in set_device_regs()