Lines Matching refs:p_hal
43 static MPP_RET set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg) in set_device_regs() argument
82 (void)p_hal; in set_device_regs()
380 static MPP_RET set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_pic_regs() argument
384 p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1; in set_pic_regs()
385 p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag) in set_pic_regs()
386 * (p_hal->pp->wFrameHeightInMbsMinus1 + 1); in set_pic_regs()
391 static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_vlc_regs() argument
395 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in set_vlc_regs()
409 p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen; in set_vlc_regs()
410 p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag; in set_vlc_regs()
411 p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id; in set_vlc_regs()
412 p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id; in set_vlc_regs()
413 p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen; in set_vlc_regs()
459 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in set_vlc_regs()
483 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in set_vlc_regs()
512 mpp_buf_slot_get_prop(p_hal->packet_slots, in set_vlc_regs()
513 p_hal->in_task->input, in set_vlc_regs()
517 p_regs->sw51.stream_len = p_hal->strm_len; in set_vlc_regs()
523 static MPP_RET set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_ref_regs() argument
530 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in set_ref_regs()
584 if (num_refs > 1 && !p_hal->pp->field_pic_flag) { in set_ref_regs()
631 static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs) in set_asic_regs() argument
637 DXVA_PicParams_H264_MVC *pp = p_hal->pp; in set_asic_regs()
638 DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0]; in set_asic_regs()
660 mpp_buf_slot_get_prop(p_hal->frame_slots, in set_asic_regs()
669 mpp_buf_slot_get_prop(p_hal->frame_slots, in set_asic_regs()
688 mpp_dev_set_reg_offset(p_hal->dev, vdpu2_ref_idx[i], val); in set_asic_regs()
704 H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv; in set_asic_regs()
706 mpp_buf_slot_get_prop(p_hal->frame_slots, in set_asic_regs()
716 mpp_buf_slot_get_prop(p_hal->frame_slots, in set_asic_regs()
721 mpp_dev_set_reg_offset(p_hal->dev, 63, ((pp->wFrameWidthInMbsMinus1 + 1) * 16)); in set_asic_regs()
731 picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1; in set_asic_regs()
735 * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384); in set_asic_regs()
740 mpp_dev_set_reg_offset(p_hal->dev, 62, offset); in set_asic_regs()
760 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in set_asic_regs()
761 if (p_hal->pp->scaleing_list_enable_flag) { in set_asic_regs()
767 temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) | in set_asic_regs()
768 (p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) | in set_asic_regs()
769 (p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) | in set_asic_regs()
770 (p_hal->qm->bScalingLists4x4[i][4 * j + 3]); in set_asic_regs()
776 temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) | in set_asic_regs()
777 (p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) | in set_asic_regs()
778 (p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) | in set_asic_regs()
779 (p_hal->qm->bScalingLists8x8[i][4 * j + 3]); in set_asic_regs()
803 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_init() local
807 MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, in vdpu2_h264d_init()
809 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t))); in vdpu2_h264d_init()
810 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu2_h264d_init()
814 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu2_h264d_init()
818 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->reg_buf[i].buf, buf_size)); in vdpu2_h264d_init()
828 if (!p_hal->fast_mode) { in vdpu2_h264d_init()
836 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); in vdpu2_h264d_init()
837 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); in vdpu2_h264d_init()
857 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_deinit() local
858 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu2_h264d_deinit()
861 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in vdpu2_h264d_deinit()
867 MPP_FREE(p_hal->reg_ctx); in vdpu2_h264d_deinit()
868 MPP_FREE(p_hal->priv); in vdpu2_h264d_deinit()
884 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_gen_regs() local
885 INP_CHECK(ret, NULL == p_hal); in vdpu2_h264d_gen_regs()
886 p_hal->in_task = &task->dec; in vdpu2_h264d_gen_regs()
889 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu2_h264d_gen_regs()
892 priv = p_hal->priv; in vdpu2_h264d_gen_regs()
893 priv->layed_id = p_hal->pp->curr_layer_id; in vdpu2_h264d_gen_regs()
895 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu2_h264d_gen_regs()
896 if (p_hal->fast_mode) { in vdpu2_h264d_gen_regs()
912 FUN_CHECK(ret = adjust_input(priv, &p_hal->slice_long[0], p_hal->pp)); in vdpu2_h264d_gen_regs()
913 FUN_CHECK(ret = set_device_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs)); in vdpu2_h264d_gen_regs()
914 FUN_CHECK(ret = set_pic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs)); in vdpu2_h264d_gen_regs()
915 FUN_CHECK(ret = set_vlc_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs)); in vdpu2_h264d_gen_regs()
916 FUN_CHECK(ret = set_ref_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs)); in vdpu2_h264d_gen_regs()
917 FUN_CHECK(ret = set_asic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs)); in vdpu2_h264d_gen_regs()
935 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_start() local
936 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu2_h264d_start()
937 H264dVdpuRegs_t *p_regs = p_hal->fast_mode ? in vdpu2_h264d_start()
946 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu2_h264d_start()
973 p_hal->pp->frame_num); in vdpu2_h264d_start()
992 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_WR, &wr_cfg); in vdpu2_h264d_start()
1002 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu2_h264d_start()
1008 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_SEND, NULL); in vdpu2_h264d_start()
1029 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_wait() local
1030 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx; in vdpu2_h264d_wait()
1031 H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)(p_hal->fast_mode ? in vdpu2_h264d_wait()
1036 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) { in vdpu2_h264d_wait()
1040 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL); in vdpu2_h264d_wait()
1045 if (p_hal->dec_cb) { in vdpu2_h264d_wait()
1052 mpp_callback(p_hal->dec_cb, ¶m); in vdpu2_h264d_wait()
1055 if (p_hal->fast_mode) { in vdpu2_h264d_wait()
1073 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_reset() local
1075 INP_CHECK(ret, NULL == p_hal); in vdpu2_h264d_reset()
1077 memset(p_hal->priv, 0, sizeof(H264dVdpuPriv_t)); in vdpu2_h264d_reset()
1092 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_flush() local
1094 INP_CHECK(ret, NULL == p_hal); in vdpu2_h264d_flush()
1109 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; in vdpu2_h264d_control() local
1111 INP_CHECK(ret, NULL == p_hal); in vdpu2_h264d_control()