Lines Matching refs:reg_buf
60 Avs2dVdpu382Buf_t reg_buf[VDPU382_FAST_REG_SET_CNT]; member
362 RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in hal_avs2d_rcb_info_update()
552 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in hal_avs2d_vdpu382_deinit()
559 MPP_FREE(reg_ctx->reg_buf[i].regs); in hal_avs2d_vdpu382_deinit()
594 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; in hal_avs2d_vdpu382_init()
600 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu382Avs2dRegSet, 1); in hal_avs2d_vdpu382_init()
601 init_common_regs(reg_ctx->reg_buf[i].regs); in hal_avs2d_vdpu382_init()
602 reg_ctx->reg_buf[i].offset_shph = AVS2_SHPH_OFFSET(i); in hal_avs2d_vdpu382_init()
603 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i); in hal_avs2d_vdpu382_init()
607 reg_ctx->regs = reg_ctx->reg_buf[0].regs; in hal_avs2d_vdpu382_init()
608 reg_ctx->shph_offset = reg_ctx->reg_buf[0].offset_shph; in hal_avs2d_vdpu382_init()
609 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst; in hal_avs2d_vdpu382_init()
698 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) { in hal_avs2d_vdpu382_gen_regs()
699 if (!reg_ctx->reg_buf[i].valid) { in hal_avs2d_vdpu382_gen_regs()
701 regs = reg_ctx->reg_buf[i].regs; in hal_avs2d_vdpu382_gen_regs()
702 reg_ctx->shph_offset = reg_ctx->reg_buf[i].offset_shph; in hal_avs2d_vdpu382_gen_regs()
703 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst; in hal_avs2d_vdpu382_gen_regs()
704 reg_ctx->regs = reg_ctx->reg_buf[i].regs; in hal_avs2d_vdpu382_gen_regs()
705 reg_ctx->reg_buf[i].valid = 1; in hal_avs2d_vdpu382_gen_regs()
883 regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs; in hal_avs2d_vdpu382_start()
1103 p_regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs; in hal_avs2d_vdpu382_wait()
1168 reg_ctx->reg_buf[task->dec.reg_index].valid = 0; in hal_avs2d_vdpu382_wait()