56 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,  in tegra_sor_writel()  function
68 	tegra_sor_writel(sor, reg, reg_val);  in tegra_sor_write_field()
128 	tegra_sor_writel(sor, PWR, reg_val);  in tegra_dc_sor_set_power_state()
162 	tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_dp_linkctl()
166 		tegra_sor_writel(sor, DP_TPG, 0x41414141);  in tegra_dc_sor_set_dp_linkctl()
172 		tegra_sor_writel(sor, DP_TPG, reg_val);  in tegra_dc_sor_set_dp_linkctl()
175 		tegra_sor_writel(sor, DP_TPG, 0x50505050);  in tegra_dc_sor_set_dp_linkctl()
201 	tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);  in tegra_dc_sor_enable_lane_sequencer()
238 		tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);  in tegra_dc_sor_power_dplanes()
257 	tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_panel_power()
263 	tegra_sor_writel(sor, PWM_DIV, pwm_div);  in tegra_dc_sor_config_pwm()
264 	tegra_sor_writel(sor, PWM_CTL,  in tegra_dc_sor_config_pwm()
301 	tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);  in tegra_dc_sor_set_dp_mode()
315 	tegra_sor_writel(sor, SUPER_STATE0, 0);  in tegra_dc_sor_super_update()
316 	tegra_sor_writel(sor, SUPER_STATE0, 1);  in tegra_dc_sor_super_update()
317 	tegra_sor_writel(sor, SUPER_STATE0, 0);  in tegra_dc_sor_super_update()
322 	tegra_sor_writel(sor, STATE0, 0);  in tegra_dc_sor_update()
323 	tegra_sor_writel(sor, STATE0, 1);  in tegra_dc_sor_update()
324 	tegra_sor_writel(sor, STATE0, 0);  in tegra_dc_sor_update()
386 	tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);  in tegra_dc_sor_set_internal_panel()
452 	tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_lane_count()
633 	tegra_sor_writel(sor, STATE1, reg_val);  in tegra_dc_sor_config_panel()
644 	tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),  in tegra_dc_sor_config_panel()
650 	tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),  in tegra_dc_sor_config_panel()
656 	tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),  in tegra_dc_sor_config_panel()
662 	tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),  in tegra_dc_sor_config_panel()
667 	tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);  in tegra_dc_sor_config_panel()
710 	tegra_sor_writel(sor, PLL0,  in tegra_dc_sor_enable_dp()
723 	tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |  in tegra_dc_sor_enable_dp()
783 	tegra_sor_writel(sor, SUPER_STATE1,  in tegra_dc_sor_attach()
797 	tegra_sor_writel(sor, SUPER_STATE1,  in tegra_dc_sor_attach()
799 	tegra_sor_writel(sor, SUPER_STATE1,  in tegra_dc_sor_attach()
837 	tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),  in tegra_dc_sor_set_lane_parm()
839 	tegra_sor_writel(sor, PR(sor->portnum),  in tegra_dc_sor_set_lane_parm()
841 	tegra_sor_writel(sor, POSTCURSOR(sor->portnum),  in tegra_dc_sor_set_lane_parm()
843 	tegra_sor_writel(sor, LVDS, 0);  in tegra_dc_sor_set_lane_parm()
882 	tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current);  in tegra_dc_sor_set_voltage_swing()
883 	tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);  in tegra_dc_sor_set_voltage_swing()
920 	tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);  in tegra_dc_sor_power_down_unused_lanes()
983 	tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |  in tegra_dc_sor_detach()
999 	tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |  in tegra_dc_sor_detach()