Lines Matching refs:tegra_sor_readl
51 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) in tegra_sor_readl() function
65 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field()
101 reg_val = tegra_sor_readl(sor, reg); in tegra_dc_sor_poll_register()
119 orig_val = tegra_sor_readl(sor, PWR); in tegra_dc_sor_set_power_state()
149 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_dp_linkctl()
220 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_dplanes()
250 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_set_panel_power()
285 reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); in tegra_dc_sor_set_dp_mode()
378 reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); in tegra_dc_sor_set_internal_panel()
395 reg_val = tegra_sor_readl(sor, CLK_CNTRL); in tegra_dc_sor_read_link_config()
398 reg_val = tegra_sor_readl(sor, in tegra_dc_sor_read_link_config()
433 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_lane_count()
479 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_up()
540 #a, a, tegra_sor_readl(sor, a)); in dump_sor_reg()
779 reg_val = tegra_sor_readl(sor, TEST); in tegra_dc_sor_attach()