681 	u32 reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
683 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
688 	       &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_enable_dc()
689 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
772 	writel(0x9f00, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
773 	writel(0x9f, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
777 	       &disp_ctrl->cmd.disp_pow_ctrl);  in tegra_dc_sor_attach()
791 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
793 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
806 	reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
807 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
809 	       &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_attach()
811 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
1004 	dc_int_mask = readl(&disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1005 	writel(0, &disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1014 	writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_detach()
1021 	writel(dc_int_mask, &disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()