1236 phy_write(struct samsung_mipi_dcphy *samsung, u32 reg, u32 val)  in phy_write()  argument
1238 	writel(val, samsung->base + reg);  in phy_write()
1241 static inline u32 phy_read(struct samsung_mipi_dcphy *samsung, u32 reg)  in phy_read()  argument
1243 	return readl(samsung->base + reg);  in phy_read()
1246 static inline void phy_update_bits(struct samsung_mipi_dcphy *samsung,  in phy_update_bits()  argument
1251 	orig = phy_read(samsung, reg);  in phy_update_bits()
1254 	phy_write(samsung, reg, tmp);  in phy_update_bits()
1257 static inline void grf_write(struct samsung_mipi_dcphy *samsung,  in grf_write()  argument
1260 	regmap_write(samsung->grf, reg, val);  in grf_write()
1264 samsung_mipi_dphy_get_timing(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dphy_get_timing()  argument
1268 	unsigned int lane_mbps = samsung->pll.rate / USEC_PER_SEC;  in samsung_mipi_dphy_get_timing()
1285 samsung_mipi_cphy_get_timing(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_cphy_get_timing()  argument
1289 	unsigned int lane_msps = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_cphy_get_timing()
1305 static void samsung_mipi_dcphy_bias_block_enable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dcphy_bias_block_enable()  argument
1307 	phy_write(samsung, BIAS_CON0, 0x0010);  in samsung_mipi_dcphy_bias_block_enable()
1308 	phy_write(samsung, BIAS_CON1, 0x0110);  in samsung_mipi_dcphy_bias_block_enable()
1309 	phy_write(samsung, BIAS_CON2, 0x3223);  in samsung_mipi_dcphy_bias_block_enable()
1311 	if (samsung->c_option)  in samsung_mipi_dcphy_bias_block_enable()
1312 		phy_update_bits(samsung, BIAS_CON4, I_MUX_SEL_MASK, I_MUX_SEL(2));  in samsung_mipi_dcphy_bias_block_enable()
1315 static void samsung_mipi_dcphy_bias_block_disable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dcphy_bias_block_disable()  argument
1319 static void samsung_mipi_dcphy_pll_configure(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dcphy_pll_configure()  argument
1321 	phy_update_bits(samsung, PLL_CON0, S_MASK | P_MASK,  in samsung_mipi_dcphy_pll_configure()
1322 			S(samsung->pll.scaler) | P(samsung->pll.prediv));  in samsung_mipi_dcphy_pll_configure()
1323 	phy_write(samsung, PLL_CON1, samsung->pll.dsm);  in samsung_mipi_dcphy_pll_configure()
1324 	phy_update_bits(samsung, PLL_CON2, M_MASK, M(samsung->pll.fbdiv));  in samsung_mipi_dcphy_pll_configure()
1326 	if (samsung->pll.ssc_en) {  in samsung_mipi_dcphy_pll_configure()
1327 		phy_write(samsung, PLL_CON3,  in samsung_mipi_dcphy_pll_configure()
1328 			  MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr));  in samsung_mipi_dcphy_pll_configure()
1329 		phy_update_bits(samsung, PLL_CON4, SSCG_EN, SSCG_EN);  in samsung_mipi_dcphy_pll_configure()
1332 	phy_write(samsung, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL);  in samsung_mipi_dcphy_pll_configure()
1333 	phy_write(samsung, PLL_CON7, PLL_LOCK_CNT(0xf000));  in samsung_mipi_dcphy_pll_configure()
1334 	phy_write(samsung, PLL_CON8, PLL_STB_CNT(0xf000));  in samsung_mipi_dcphy_pll_configure()
1338 samsung_mipi_dphy_clk_lane_timing_init(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dphy_clk_lane_timing_init()  argument
1341 	unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_dphy_clk_lane_timing_init()
1344 	timing = samsung_mipi_dphy_get_timing(samsung);  in samsung_mipi_dphy_clk_lane_timing_init()
1345 	phy_write(samsung, DPHY_MC_GNR_CON0, 0xf000);  in samsung_mipi_dphy_clk_lane_timing_init()
1351 	res_up = samsung->pdata->dphy_hs_drv_res_cfg->clk_hs_drv_up_ohm;  in samsung_mipi_dphy_clk_lane_timing_init()
1352 	res_down = samsung->pdata->dphy_hs_drv_res_cfg->clk_hs_drv_down_ohm;  in samsung_mipi_dphy_clk_lane_timing_init()
1355 	phy_write(samsung, DPHY_MC_ANA_CON0, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1358 		phy_write(samsung, DPHY_MC_ANA_CON1, 0x0001);  in samsung_mipi_dphy_clk_lane_timing_init()
1370 	phy_write(samsung, DPHY_MC_TIME_CON0, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1373 	phy_write(samsung, DPHY_MC_TIME_CON1, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1376 	phy_write(samsung, DPHY_MC_TIME_CON2, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1379 	phy_write(samsung, DPHY_MC_TIME_CON3, val);  in samsung_mipi_dphy_clk_lane_timing_init()
1382 	phy_write(samsung, DPHY_MC_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_clk_lane_timing_init()
1389 		phy_write(samsung, DPHY_MC_DESKEW_CON0, 0x9cb1);  in samsung_mipi_dphy_clk_lane_timing_init()
1393 samsung_mipi_dphy_data_lane_timing_init(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dphy_data_lane_timing_init()  argument
1396 	unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_dphy_data_lane_timing_init()
1399 	timing = samsung_mipi_dphy_get_timing(samsung);  in samsung_mipi_dphy_data_lane_timing_init()
1405 	res_up = samsung->pdata->dphy_hs_drv_res_cfg->data_hs_drv_up_ohm;  in samsung_mipi_dphy_data_lane_timing_init()
1406 	res_down = samsung->pdata->dphy_hs_drv_res_cfg->data_hs_drv_down_ohm;  in samsung_mipi_dphy_data_lane_timing_init()
1409 	phy_write(samsung, COMBO_MD0_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1410 	phy_write(samsung, COMBO_MD1_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1411 	phy_write(samsung, COMBO_MD2_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1412 	phy_write(samsung, DPHY_MD3_ANA_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1415 		phy_write(samsung, COMBO_MD0_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1416 		phy_write(samsung, COMBO_MD1_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1417 		phy_write(samsung, COMBO_MD2_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1418 		phy_write(samsung, DPHY_MD3_ANA_CON1, 0x0001);  in samsung_mipi_dphy_data_lane_timing_init()
1431 	phy_write(samsung, COMBO_MD0_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1432 	phy_write(samsung, COMBO_MD1_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1433 	phy_write(samsung, COMBO_MD2_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1434 	phy_write(samsung, DPHY_MD3_TIME_CON0, val);  in samsung_mipi_dphy_data_lane_timing_init()
1437 	phy_write(samsung, COMBO_MD0_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1438 	phy_write(samsung, COMBO_MD1_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1439 	phy_write(samsung, COMBO_MD2_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1440 	phy_write(samsung, DPHY_MD3_TIME_CON1, val);  in samsung_mipi_dphy_data_lane_timing_init()
1443 	phy_write(samsung, COMBO_MD0_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1444 	phy_write(samsung, COMBO_MD1_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1445 	phy_write(samsung, COMBO_MD2_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1446 	phy_write(samsung, DPHY_MD3_TIME_CON2, val);  in samsung_mipi_dphy_data_lane_timing_init()
1450 	phy_write(samsung, COMBO_MD0_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1451 	phy_write(samsung, COMBO_MD1_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1452 	phy_write(samsung, COMBO_MD2_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1453 	phy_write(samsung, DPHY_MD3_TIME_CON3, val);  in samsung_mipi_dphy_data_lane_timing_init()
1456 	phy_write(samsung, COMBO_MD0_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1457 	phy_write(samsung, COMBO_MD1_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1458 	phy_write(samsung, COMBO_MD2_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1459 	phy_write(samsung, DPHY_MD3_TIME_CON4, 0x1f4);  in samsung_mipi_dphy_data_lane_timing_init()
1462 static void samsung_mipi_dcphy_pll_enable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dcphy_pll_enable()  argument
1467 	phy_update_bits(samsung, PLL_CON0, PLL_EN, PLL_EN);  in samsung_mipi_dcphy_pll_enable()
1469 	ret = readl_poll_timeout(samsung->base + PLL_STAT0,  in samsung_mipi_dcphy_pll_enable()
1472 		dev_err(samsung->dev, "DC-PHY pll is not locked\n");  in samsung_mipi_dcphy_pll_enable()
1475 static void samsung_mipi_dcphy_pll_disable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dcphy_pll_disable()  argument
1477 	phy_update_bits(samsung, PLL_CON0, PLL_EN, 0);  in samsung_mipi_dcphy_pll_disable()
1480 static void samsung_mipi_dphy_lane_enable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dphy_lane_enable()  argument
1482 	phy_write(samsung, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1483 	phy_update_bits(samsung, DPHY_MC_GNR_CON0, PHY_ENABLE, PHY_ENABLE);  in samsung_mipi_dphy_lane_enable()
1485 	switch (samsung->lanes) {  in samsung_mipi_dphy_lane_enable()
1487 		phy_write(samsung, DPHY_MD3_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1488 		phy_update_bits(samsung, DPHY_MD3_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1492 		phy_write(samsung, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1493 		phy_update_bits(samsung, COMBO_MD2_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1497 		phy_write(samsung, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1498 		phy_update_bits(samsung, COMBO_MD1_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1503 		phy_write(samsung, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_dphy_lane_enable()
1504 		phy_update_bits(samsung, COMBO_MD0_GNR_CON0,  in samsung_mipi_dphy_lane_enable()
1510 static void samsung_mipi_cphy_timing_init(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_cphy_timing_init()  argument
1513 	unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC);  in samsung_mipi_cphy_timing_init()
1516 	timing = samsung_mipi_cphy_get_timing(samsung);  in samsung_mipi_cphy_timing_init()
1527 	phy_write(samsung, COMBO_MD0_TIME_CON0, val);  in samsung_mipi_cphy_timing_init()
1528 	phy_write(samsung, COMBO_MD1_TIME_CON0, val);  in samsung_mipi_cphy_timing_init()
1529 	phy_write(samsung, COMBO_MD2_TIME_CON0, val);  in samsung_mipi_cphy_timing_init()
1532 	phy_write(samsung, COMBO_MD0_TIME_CON1, val);  in samsung_mipi_cphy_timing_init()
1533 	phy_write(samsung, COMBO_MD1_TIME_CON1, val);  in samsung_mipi_cphy_timing_init()
1534 	phy_write(samsung, COMBO_MD2_TIME_CON1, val);  in samsung_mipi_cphy_timing_init()
1537 	phy_write(samsung, DPHY_MD3_TIME_CON2, val);  in samsung_mipi_cphy_timing_init()
1538 	phy_write(samsung, COMBO_MD0_TIME_CON2, val);  in samsung_mipi_cphy_timing_init()
1539 	phy_write(samsung, COMBO_MD1_TIME_CON2, val);  in samsung_mipi_cphy_timing_init()
1540 	phy_write(samsung, COMBO_MD2_TIME_CON2, val);  in samsung_mipi_cphy_timing_init()
1544 	phy_write(samsung, COMBO_MD0_TIME_CON3, val);  in samsung_mipi_cphy_timing_init()
1545 	phy_write(samsung, COMBO_MD1_TIME_CON3, val);  in samsung_mipi_cphy_timing_init()
1546 	phy_write(samsung, COMBO_MD2_TIME_CON3, val);  in samsung_mipi_cphy_timing_init()
1549 	phy_write(samsung, COMBO_MD0_TIME_CON4, 0x1f4);  in samsung_mipi_cphy_timing_init()
1550 	phy_write(samsung, COMBO_MD1_TIME_CON4, 0x1f4);  in samsung_mipi_cphy_timing_init()
1551 	phy_write(samsung, COMBO_MD2_TIME_CON4, 0x1f4);  in samsung_mipi_cphy_timing_init()
1556 static void samsung_mipi_cphy_lane_enable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_cphy_lane_enable()  argument
1558 	phy_write(samsung, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_cphy_lane_enable()
1559 	phy_write(samsung, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_cphy_lane_enable()
1560 	phy_write(samsung, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000));  in samsung_mipi_cphy_lane_enable()
1562 	phy_update_bits(samsung, COMBO_MD0_GNR_CON0, PHY_ENABLE, PHY_ENABLE);  in samsung_mipi_cphy_lane_enable()
1563 	phy_update_bits(samsung, COMBO_MD1_GNR_CON0, PHY_ENABLE, PHY_ENABLE);  in samsung_mipi_cphy_lane_enable()
1564 	phy_update_bits(samsung, COMBO_MD2_GNR_CON0, PHY_ENABLE, PHY_ENABLE);  in samsung_mipi_cphy_lane_enable()
1568 samsung_mipi_dcphy_hs_vreg_amp_config(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dcphy_hs_vreg_amp_config()  argument
1570 	phy_write(samsung, DPHY_MC_ANA_CON2, HS_VREG_AMP_ICON(2));  in samsung_mipi_dcphy_hs_vreg_amp_config()
1573 static void samsung_mipi_dphy_power_on(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dphy_power_on()  argument
1575 	reset_assert(&samsung->m_phy_rst);  in samsung_mipi_dphy_power_on()
1577 	samsung_mipi_dcphy_bias_block_enable(samsung);  in samsung_mipi_dphy_power_on()
1578 	samsung_mipi_dcphy_pll_configure(samsung);  in samsung_mipi_dphy_power_on()
1579 	samsung_mipi_dphy_clk_lane_timing_init(samsung);  in samsung_mipi_dphy_power_on()
1580 	samsung_mipi_dphy_data_lane_timing_init(samsung);  in samsung_mipi_dphy_power_on()
1581 	samsung_mipi_dcphy_pll_enable(samsung);  in samsung_mipi_dphy_power_on()
1582 	samsung_mipi_dphy_lane_enable(samsung);  in samsung_mipi_dphy_power_on()
1584 	reset_deassert(&samsung->m_phy_rst);  in samsung_mipi_dphy_power_on()
1590 static void samsung_mipi_cphy_power_on(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_cphy_power_on()  argument
1592 	grf_write(samsung, MIPI_DCPHY_GRF_CON0, M_CPHY_MODE);  in samsung_mipi_cphy_power_on()
1593 	reset_assert(&samsung->m_phy_rst);  in samsung_mipi_cphy_power_on()
1595 	samsung_mipi_dcphy_bias_block_enable(samsung);  in samsung_mipi_cphy_power_on()
1596 	samsung_mipi_dcphy_hs_vreg_amp_config(samsung);  in samsung_mipi_cphy_power_on()
1597 	samsung_mipi_dcphy_pll_configure(samsung);  in samsung_mipi_cphy_power_on()
1598 	samsung_mipi_cphy_timing_init(samsung);  in samsung_mipi_cphy_power_on()
1599 	samsung_mipi_dcphy_pll_enable(samsung);  in samsung_mipi_cphy_power_on()
1600 	samsung_mipi_cphy_lane_enable(samsung);  in samsung_mipi_cphy_power_on()
1602 	reset_deassert(&samsung->m_phy_rst);  in samsung_mipi_cphy_power_on()
1605 static void samsung_mipi_dphy_lane_disable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_dphy_lane_disable()  argument
1607 	phy_update_bits(samsung, DPHY_MC_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1608 	phy_update_bits(samsung, COMBO_MD0_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1609 	phy_update_bits(samsung, COMBO_MD1_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1610 	phy_update_bits(samsung, COMBO_MD2_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1611 	phy_update_bits(samsung, DPHY_MD3_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_dphy_lane_disable()
1614 static void samsung_mipi_cphy_lane_disable(struct samsung_mipi_dcphy *samsung)  in samsung_mipi_cphy_lane_disable()  argument
1616 	phy_update_bits(samsung, COMBO_MD0_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_cphy_lane_disable()
1617 	phy_update_bits(samsung, COMBO_MD1_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_cphy_lane_disable()
1618 	phy_update_bits(samsung, COMBO_MD2_GNR_CON0, PHY_ENABLE, 0);  in samsung_mipi_cphy_lane_disable()
1623 	struct samsung_mipi_dcphy *samsung = dev_get_priv(phy->dev);  in samsung_mipi_dcphy_power_on()  local
1625 	if (samsung->mode == PHY_MODE_MIPI_DPHY)  in samsung_mipi_dcphy_power_on()
1626 		samsung_mipi_dphy_power_on(samsung);  in samsung_mipi_dcphy_power_on()
1628 		samsung_mipi_cphy_power_on(samsung);  in samsung_mipi_dcphy_power_on()
1635 	struct samsung_mipi_dcphy *samsung = dev_get_priv(phy->dev);  in samsung_mipi_dcphy_power_off()  local
1637 	if (samsung->mode == PHY_MODE_MIPI_DPHY)  in samsung_mipi_dcphy_power_off()
1638 		samsung_mipi_dphy_lane_disable(samsung);  in samsung_mipi_dcphy_power_off()
1640 		samsung_mipi_cphy_lane_disable(samsung);  in samsung_mipi_dcphy_power_off()
1642 	samsung_mipi_dcphy_pll_disable(samsung);  in samsung_mipi_dcphy_power_off()
1643 	samsung_mipi_dcphy_bias_block_disable(samsung);  in samsung_mipi_dcphy_power_off()
1649 samsung_mipi_dcphy_pll_ssc_modulation_calc(struct samsung_mipi_dcphy *samsung,  in samsung_mipi_dcphy_pll_ssc_modulation_calc()  argument
1692 		dev_info(samsung->dev, "mfr=%d, mrr=%d, MF=%llukHz, MR=%lluppm\n",  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1699 	dev_info(samsung->dev, "%s: failed to calc ssc parameter mfr and mrr\n", __func__);  in samsung_mipi_dcphy_pll_ssc_modulation_calc()
1705 samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung,  in samsung_mipi_dcphy_pll_round_rate()  argument
1709 	u32 max_fout = samsung->c_option ?  in samsung_mipi_dcphy_pll_round_rate()
1710 		       samsung->pdata->cphy_tx_max_ksps_per_lane :  in samsung_mipi_dcphy_pll_round_rate()
1711 		       samsung->pdata->dphy_tx_max_kbps_per_lane;  in samsung_mipi_dcphy_pll_round_rate()
1725 		dev_err(samsung->dev, "prate of pll can not be set zero\n");  in samsung_mipi_dcphy_pll_round_rate()
1784 					ret = samsung_mipi_dcphy_pll_ssc_modulation_calc(samsung,  in samsung_mipi_dcphy_pll_round_rate()
1822 	struct samsung_mipi_dcphy *samsung = dev_get_priv(phy->dev);  in samsung_mipi_dcphy_set_pll()  local
1829 	samsung->c_option = (samsung->mode == PHY_MODE_MIPI_DPHY) ? false : true;  in samsung_mipi_dcphy_set_pll()
1830 	fout = samsung_mipi_dcphy_pll_round_rate(samsung, fin, rate, &prediv,  in samsung_mipi_dcphy_set_pll()
1834 		samsung->pll.prediv = prediv;  in samsung_mipi_dcphy_set_pll()
1835 		samsung->pll.fbdiv = fbdiv;  in samsung_mipi_dcphy_set_pll()
1836 		samsung->pll.dsm = dsm;  in samsung_mipi_dcphy_set_pll()
1837 		samsung->pll.scaler = scaler;  in samsung_mipi_dcphy_set_pll()
1838 		samsung->pll.rate = fout;  in samsung_mipi_dcphy_set_pll()
1841 			samsung->pll.ssc_en = true;  in samsung_mipi_dcphy_set_pll()
1842 			samsung->pll.mfr = mfr;  in samsung_mipi_dcphy_set_pll()
1843 			samsung->pll.mrr = mrr;  in samsung_mipi_dcphy_set_pll()
1853 	struct samsung_mipi_dcphy *samsung = dev_get_priv(phy->dev);  in samsung_mipi_dcphy_set_mode()  local
1855 	samsung->mode = mode;  in samsung_mipi_dcphy_set_mode()
1862 	struct samsung_mipi_dcphy *samsung = dev_get_priv(dev);  in samsung_mipi_dcphy_probe()  local
1876 	samsung->pdata = (struct samsung_mipi_dcphy_plat_data *)phy->data;  in samsung_mipi_dcphy_probe()
1877 	samsung->lanes = ofnode_read_u32_default(dev->node, "samsung,lanes", 4);  in samsung_mipi_dcphy_probe()
1879 	samsung->base = dev_read_addr_ptr(dev);  in samsung_mipi_dcphy_probe()
1880 	if (IS_ERR(samsung->base)) {  in samsung_mipi_dcphy_probe()
1882 		return PTR_ERR(samsung->base);  in samsung_mipi_dcphy_probe()
1888 		samsung->grf = syscon_get_regmap(syscon);  in samsung_mipi_dcphy_probe()
1889 		if (!samsung->grf)  in samsung_mipi_dcphy_probe()
1893 	ret = reset_get_by_name(dev, "m_phy", &samsung->m_phy_rst);  in samsung_mipi_dcphy_probe()
1895 		ret = reset_get_by_name(dev, "phy", &samsung->m_phy_rst);  in samsung_mipi_dcphy_probe()