5268 	u32 win_offset = win->reg_offset;  in vop2_setup_scale()  local
5369 			vop2_writel(vop2, RK3576_CLUSTER0_WIN0_ZME_DERING_PARA + win_offset,  in vop2_setup_scale()
5371 			vop2_mask_write(vop2, RK3576_CLUSTER0_WIN0_ZME_CTRL + win_offset,  in vop2_setup_scale()
5380 		vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
5384 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5386 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5388 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5391 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5394 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5398 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5401 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5407 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5409 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5411 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5413 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5416 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5418 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5420 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5422 			vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,  in vop2_setup_scale()
5426 		vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
5430 			vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
5432 			vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
5434 			vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
5438 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
5440 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_setup_scale()
5443 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
5445 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
5448 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
5451 		vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,  in vop2_setup_scale()
5459 	u32 win_offset = win->reg_offset;  in vop2_axi_config()  local
5462 		vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK,  in vop2_axi_config()
5464 		vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK,  in vop2_axi_config()
5466 		vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK,  in vop2_axi_config()
5469 		vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK,  in vop2_axi_config()
5471 		vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK,  in vop2_axi_config()
5473 		vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK,  in vop2_axi_config()
5514 	u32 win_offset = win->reg_offset;  in vop2_set_cluster_win()  local
5552 		vop2_mask_write(vop2, RK3576_CLUSTER0_PORT_SEL + win_offset,  in vop2_set_cluster_win()
5562 		vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset,  in vop2_set_cluster_win()
5565 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset,  in vop2_set_cluster_win()
5568 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset,  in vop2_set_cluster_win()
5570 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir);  in vop2_set_cluster_win()
5571 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset,  in vop2_set_cluster_win()
5574 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info);  in vop2_set_cluster_win()
5575 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info);  in vop2_set_cluster_win()
5576 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st);  in vop2_set_cluster_win()
5580 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,  in vop2_set_cluster_win()
5583 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK,  in vop2_set_cluster_win()
5587 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,  in vop2_set_cluster_win()
5590 	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false);  in vop2_set_cluster_win()
5591 	vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false);  in vop2_set_cluster_win()
5617 	u32 win_offset = win->reg_offset;  in vop2_set_smart_win()  local
5672 		vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset,  in vop2_set_smart_win()
5675 		vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset,  in vop2_set_smart_win()
5684 			vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset,  in vop2_set_smart_win()
5696 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK,  in vop2_set_smart_win()
5699 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_set_smart_win()
5703 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,  in vop2_set_smart_win()
5707 		vop2_writel(vop2, RK3576_ESMART0_ALPHA_MAP + win_offset, 0x8000ff00);  in vop2_set_smart_win()
5709 	vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir);  in vop2_set_smart_win()
5710 	vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset,  in vop2_set_smart_win()
5713 	vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset,  in vop2_set_smart_win()
5715 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset,  in vop2_set_smart_win()
5717 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st);  in vop2_set_smart_win()
5721 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK,  in vop2_set_smart_win()
5724 	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK,  in vop2_set_smart_win()
5728 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,  in vop2_set_smart_win()
5731 	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,  in vop2_set_smart_win()