Lines Matching refs:vp_offset
1872 u32 vp_offset = crtc_id * 0x100; in rk3568_vop2_load_lut() local
1882 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3568_vop2_load_lut()
1889 u32 vp_offset = crtc_id * 0x100; in rk3588_vop2_load_lut() local
1904 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1906 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1986 u32 vp_offset = cstate->crtc_id * 0x100; in rockchip_vop2_cubic_lut_init() local
2021 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, in rockchip_vop2_cubic_lut_init()
2025 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
2027 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
2037 u32 vp_offset = crtc_id * 0x100; in vop2_bcsh_reg_update() local
2039 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, in vop2_bcsh_reg_update()
2041 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, in vop2_bcsh_reg_update()
2044 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, in vop2_bcsh_reg_update()
2046 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, in vop2_bcsh_reg_update()
2050 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
2055 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2058 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2060 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2063 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
2065 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
2067 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2070 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
2203 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_config() local
2239 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); in vop2_post_config()
2243 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); in vop2_post_config()
2246 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); in vop2_post_config()
2249 vop2_mask_write(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, in vop2_post_config()
2258 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); in vop2_post_config()
2280 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_acm_config() local
2287 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_acm_config()
2382 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_csc_config() local
2424 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2445 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2449 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2451 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2453 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
3216 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_acm_init() local
3234 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in rockchip_vop2_acm_init()
3642 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3588_vop2_if_cfg() local
3727 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3729 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3753 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3755 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3761 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3588_vop2_if_cfg()
3764 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3877 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
3879 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
3891 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3576_vop2_if_cfg() local
3965 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3968 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4063 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4065 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4071 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4074 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4195 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3568_vop2_setup_dual_channel_if() local
4210 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4213 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4353 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3562_vop2_if_cfg() local
4393 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3562_vop2_if_cfg()
4395 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3562_vop2_if_cfg()
4441 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_color_swap() local
4456 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in vop2_post_color_swap()
4756 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_mode_setup() local
4758 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4760 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4762 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_mode_setup()
4764 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_mode_setup()
4766 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_mode_setup()
4768 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_mode_setup()
4770 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_mode_setup()
4778 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_bypass_mode_setup() local
4780 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4782 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4784 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_bypass_mode_setup()
4786 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_bypass_mode_setup()
4788 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_bypass_mode_setup()
4790 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_bypass_mode_setup()
4792 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_bypass_mode_setup()
4802 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_send_mcu_cmd() local
4815 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4817 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
4820 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4824 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4826 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
4831 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4854 u32 vp_offset = crtc_id * 0x100; in vop2_dither_setup() local
4860 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4862 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4870 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4872 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4887 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4897 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4908 vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_0 + vp_offset, 0x00000000); in vop2_dither_setup()
4909 vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_1 + vp_offset, 0x01000100); in vop2_dither_setup()
4910 vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_2 + vp_offset, 0x04030100); in vop2_dither_setup()
4913 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4916 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4918 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, DITHER_DOWN_SEL_MASK, in vop2_dither_setup()
4921 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4923 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, DITHER_DOWN_SEL_MASK, in vop2_dither_setup()
4946 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_init() local
4996 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
4998 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, POST_URGENCY_THL_MASK, in rockchip_vop2_init()
5000 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, POST_URGENCY_THH_MASK, in rockchip_vop2_init()
5041 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, in rockchip_vop2_init()
5054 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, in rockchip_vop2_init()
5058 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); in rockchip_vop2_init()
5061 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); in rockchip_vop2_init()
5067 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, in rockchip_vop2_init()
5071 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); in rockchip_vop2_init()
5072 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5074 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5076 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5081 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5083 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5087 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, in rockchip_vop2_init()
5095 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5098 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5102 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
5105 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
5116 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); in rockchip_vop2_init()
5124 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5128 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5251 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5876 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_enable() local
5879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5891 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5986 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_disable() local
5989 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_disable()
6233 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_apply_soft_te() local
6237 ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val, in rockchip_vop2_apply_soft_te()
6247 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_apply_soft_te()