1661 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)  in vop2_writel()  function
2021 	vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset,  in rockchip_vop2_cubic_lut_init()
2169 	vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);  in vop2_setup_dly_for_vp()
2192 	vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);  in vop3_setup_pipe_dly()
2239 	vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val);  in vop2_post_config()
2243 	vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val);  in vop2_post_config()
2246 	vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val);  in vop2_post_config()
2258 		vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);  in vop2_post_config()
3155 		vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0);  in vop2_global_initial()
3164 		vop2_writel(vop2, 0xca0, 0xc8);  in vop2_global_initial()
3165 		vop2_writel(vop2, 0xca4, 0x01000100);  in vop2_global_initial()
3166 		vop2_writel(vop2, 0xca8, 0x03ff0100);  in vop2_global_initial()
3167 		vop2_writel(vop2, 0xda0, 0xc8);  in vop2_global_initial()
3168 		vop2_writel(vop2, 0xda4, 0x01000100);  in vop2_global_initial()
3169 		vop2_writel(vop2, 0xda8, 0x03ff0100);  in vop2_global_initial()
4529 		vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++);  in vop2_load_pps()
4698 	vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);  in vop2_dsc_enable()
4703 	vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);  in vop2_dsc_enable()
4908 			vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_0 + vp_offset, 0x00000000);  in vop2_dither_setup()
4909 			vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_1 + vp_offset, 0x01000100);  in vop2_dither_setup()
4910 			vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_2 + vp_offset, 0x04030100);  in vop2_dither_setup()
5054 	vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset,  in rockchip_vop2_init()
5058 	vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val);  in rockchip_vop2_init()
5061 	vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val);  in rockchip_vop2_init()
5067 		vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset,  in rockchip_vop2_init()
5071 		vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val);  in rockchip_vop2_init()
5087 	vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset,  in rockchip_vop2_init()
5116 	vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val);  in rockchip_vop2_init()
5121 		vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val);  in rockchip_vop2_init()
5250 		vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rockchip_vop2_init()
5369 			vop2_writel(vop2, RK3576_CLUSTER0_WIN0_ZME_DERING_PARA + win_offset,  in vop2_setup_scale()
5380 		vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
5426 		vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,  in vop2_setup_scale()
5570 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir);  in vop2_set_cluster_win()
5571 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset,  in vop2_set_cluster_win()
5574 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info);  in vop2_set_cluster_win()
5575 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info);  in vop2_set_cluster_win()
5576 	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st);  in vop2_set_cluster_win()
5707 		vop2_writel(vop2, RK3576_ESMART0_ALPHA_MAP + win_offset, 0x8000ff00);  in vop2_set_smart_win()
5709 	vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir);  in vop2_set_smart_win()
5710 	vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset,  in vop2_set_smart_win()
5713 	vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset,  in vop2_set_smart_win()
5715 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset,  in vop2_set_smart_win()
5717 	vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st);  in vop2_set_smart_win()
5885 	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rockchip_vop2_enable()
5915 		vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rk3588_vop2_post_enable()
5953 		vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rk3576_vop2_post_enable()
5995 	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);  in rockchip_vop2_disable()
6383 		vop2_writel(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, 0xffffffff);  in rk3528_setup_overlay()