Lines Matching refs:vop2_mask_write
1672 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, in vop2_mask_write() function
1875 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3568_vop2_load_lut()
1882 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3568_vop2_load_lut()
1893 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3588_vop2_load_lut()
1897 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3588_vop2_load_lut()
1904 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1906 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
2023 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, in rockchip_vop2_cubic_lut_init()
2025 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
2027 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
2039 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, in vop2_bcsh_reg_update()
2041 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, in vop2_bcsh_reg_update()
2044 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, in vop2_bcsh_reg_update()
2046 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, in vop2_bcsh_reg_update()
2050 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
2055 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2058 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2060 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2063 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
2065 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
2067 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2070 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
2167 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, in vop2_setup_dly_for_vp()
2190 vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100, in vop3_setup_pipe_dly()
2249 vop2_mask_write(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, in vop2_post_config()
2287 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_acm_config()
2424 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2445 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2449 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2451 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2453 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2517 vop2_mask_write(vop2, RK3576_SYS_CLUSTER_PD_CTRL, EN_MASK, in rk3576_vop2_power_domain_on()
2520 vop2_mask_write(vop2, RK3576_SYS_ESMART_PD_CTRL, EN_MASK, in rk3576_vop2_power_domain_on()
2567 vop2_mask_write(vop2, RK3588_SYS_PD_CTRL, EN_MASK, in rk3588_vop2_power_domain_on()
3039 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, in vop2_global_initial()
3083 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, in vop2_global_initial()
3085 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in vop2_global_initial()
3118 vop2_mask_write(vop2, RK3576_SYS_ESMART_PD_CTRL, in vop2_global_initial()
3123 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in vop2_global_initial()
3131 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, in vop2_global_initial()
3134 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK, in vop2_global_initial()
3150 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in vop2_global_initial()
3161 vop2_mask_write(vop2, RK3576_SYS_MMU_CTRL, EN_MASK, RKMMU_V2_EN_SHIFT, 1, true); in vop2_global_initial()
3172 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, in vop2_global_initial()
3176 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, INTERLACE_FRM_REG_DONE_MASK, in vop2_global_initial()
3234 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in rockchip_vop2_acm_init()
3684 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
3691 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
3696 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, RK3588_BT1120_YC_SWAP_SHIFT, in rk3588_vop2_if_cfg()
3701 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
3706 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, RK3588_BT656_YC_SWAP_SHIFT, in rk3588_vop2_if_cfg()
3717 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3720 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, in rk3588_vop2_if_cfg()
3722 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); in rk3588_vop2_if_cfg()
3723 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3727 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3729 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3742 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3745 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, in rk3588_vop2_if_cfg()
3747 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3749 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3753 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3755 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3761 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3588_vop2_if_cfg()
3764 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3769 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3773 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3777 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3781 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3790 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, in rk3588_vop2_if_cfg()
3792 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
3794 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3797 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3805 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, in rk3588_vop2_if_cfg()
3807 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3809 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3812 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3820 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, in rk3588_vop2_if_cfg()
3822 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
3824 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3827 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3842 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, in rk3588_vop2_if_cfg()
3844 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3846 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3849 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3864 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
3866 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, in rk3588_vop2_if_cfg()
3871 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3873 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, in rk3588_vop2_if_cfg()
3877 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
3879 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
3965 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3968 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3973 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
3976 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3978 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3980 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3982 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
3984 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
3992 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
3995 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3997 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3999 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4001 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4003 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4008 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4014 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4017 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4019 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4021 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4023 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4025 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4030 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4035 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4038 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4041 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4043 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4045 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4047 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4055 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4059 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4063 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4065 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4071 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4074 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4078 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4082 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4086 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4090 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4099 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4102 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4105 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4107 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4109 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4111 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4113 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4118 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4121 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4124 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4126 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4128 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4130 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4132 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4137 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4140 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4143 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4145 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4147 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4149 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4154 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4157 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4160 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4162 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4164 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4166 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4171 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4174 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4177 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4179 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4181 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4183 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4199 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4201 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4204 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4210 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4213 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4218 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4220 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4239 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
4241 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4243 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4250 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
4252 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, in rk3568_vop2_if_cfg()
4254 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4261 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3568_vop2_if_cfg()
4263 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4270 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3568_vop2_if_cfg()
4272 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4274 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4276 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4281 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, in rk3568_vop2_if_cfg()
4283 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4285 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4287 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4293 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3568_vop2_if_cfg()
4295 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4297 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4299 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_MIPI_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4304 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, in rk3568_vop2_if_cfg()
4306 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4308 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4310 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_MIPI_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4321 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, in rk3568_vop2_if_cfg()
4323 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4325 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4327 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_EDP_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4332 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3568_vop2_if_cfg()
4334 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4336 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4338 vop2_mask_write(vop2, RK3568_DSP_IF_POL, in rk3568_vop2_if_cfg()
4361 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3562_vop2_if_cfg()
4363 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
4367 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
4372 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3562_vop2_if_cfg()
4374 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
4376 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
4378 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
4383 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3562_vop2_if_cfg()
4385 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
4387 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
4389 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
4393 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3562_vop2_if_cfg()
4395 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3562_vop2_if_cfg()
4415 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3528_vop2_if_cfg()
4417 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3528_vop2_if_cfg()
4422 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3528_vop2_if_cfg()
4424 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3528_vop2_if_cfg()
4426 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3528_vop2_if_cfg()
4428 vop2_mask_write(vop2, RK3568_DSP_IF_POL, in rk3528_vop2_if_cfg()
4456 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in vop2_post_color_swap()
4572 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
4574 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, in vop2_dsc_enable()
4587 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, in vop2_dsc_enable()
4590 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, in vop2_dsc_enable()
4595 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, in vop2_dsc_enable()
4597 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, in vop2_dsc_enable()
4599 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, in vop2_dsc_enable()
4601 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, in vop2_dsc_enable()
4603 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, in vop2_dsc_enable()
4605 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
4607 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, in vop2_dsc_enable()
4659 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, in vop2_dsc_enable()
4661 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, in vop2_dsc_enable()
4677 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, in vop2_dsc_enable()
4683 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, in vop2_dsc_enable()
4686 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, in vop2_dsc_enable()
4688 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, in vop2_dsc_enable()
4692 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, in vop2_dsc_enable()
4758 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4760 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4762 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_mode_setup()
4764 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_mode_setup()
4766 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_mode_setup()
4768 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_mode_setup()
4770 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_mode_setup()
4780 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4782 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4784 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_bypass_mode_setup()
4786 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_bypass_mode_setup()
4788 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_bypass_mode_setup()
4790 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_bypass_mode_setup()
4792 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_bypass_mode_setup()
4815 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4817 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
4820 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4824 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4826 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
4831 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4860 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4862 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4870 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4872 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4887 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4897 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4913 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4916 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4918 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, DITHER_DOWN_SEL_MASK, in vop2_dither_setup()
4921 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4923 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, DITHER_DOWN_SEL_MASK, in vop2_dither_setup()
4979 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, in rockchip_vop2_init()
4983 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
4985 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
4992 vop2_mask_write(vop2, RK3576_SYS_AXI_HURRY_CTRL0_IMD, EN_MASK, in rockchip_vop2_init()
4994 vop2_mask_write(vop2, RK3576_SYS_AXI_HURRY_CTRL1_IMD, EN_MASK, in rockchip_vop2_init()
4996 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
4998 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, POST_URGENCY_THL_MASK, in rockchip_vop2_init()
5000 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, POST_URGENCY_THH_MASK, in rockchip_vop2_init()
5041 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, in rockchip_vop2_init()
5049 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
5072 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5074 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5076 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5081 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5083 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5095 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5098 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5102 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
5105 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
5109 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, in rockchip_vop2_init()
5118 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, in rockchip_vop2_init()
5124 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5128 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5244 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, in rockchip_vop2_init()
5246 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, in rockchip_vop2_init()
5251 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5371 vop2_mask_write(vop2, RK3576_CLUSTER0_WIN0_ZME_CTRL + win_offset, in vop2_setup_scale()
5384 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5386 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5388 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5391 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5394 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5398 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5401 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5407 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5409 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5411 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5413 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5416 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5418 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5420 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5422 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5430 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5432 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5434 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5438 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5440 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5443 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5445 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5448 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5451 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5462 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, in vop2_axi_config()
5464 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, in vop2_axi_config()
5466 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, in vop2_axi_config()
5469 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, in vop2_axi_config()
5471 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, in vop2_axi_config()
5473 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, in vop2_axi_config()
5552 vop2_mask_write(vop2, RK3576_CLUSTER0_PORT_SEL + win_offset, in vop2_set_cluster_win()
5562 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset, in vop2_set_cluster_win()
5565 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, in vop2_set_cluster_win()
5568 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, in vop2_set_cluster_win()
5580 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
5583 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, in vop2_set_cluster_win()
5587 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
5590 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); in vop2_set_cluster_win()
5591 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); in vop2_set_cluster_win()
5672 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, in vop2_set_smart_win()
5675 vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset, in vop2_set_smart_win()
5684 vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset, in vop2_set_smart_win()
5696 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, in vop2_set_smart_win()
5699 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_set_smart_win()
5703 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_set_smart_win()
5721 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, in vop2_set_smart_win()
5724 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, in vop2_set_smart_win()
5728 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
5731 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
5862 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, in vop2_dsc_cfg_done()
5864 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, in vop2_dsc_cfg_done()
5867 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, in vop2_dsc_cfg_done()
5879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5891 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5907 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, in rk3588_vop2_post_enable()
5911 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, in rk3588_vop2_post_enable()
5941 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5945 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5949 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5989 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_disable()
6247 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_apply_soft_te()
6349 vop2_mask_write(vop2, RK3528_OVL_SYS_CLUSTER0_CTRL, CLUSTER_DLY_NUM_MASK, in rk3528_setup_win_dly()
6353 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6357 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART1_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6361 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART2_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6365 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART3_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6391 vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, in rk3528_setup_overlay()
6401 vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL, in rk3528_setup_overlay()
6421 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6425 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6429 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM1, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6433 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM1, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6437 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6441 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6446 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6451 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6475 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, in rk3568_setup_overlay()
6490 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, in rk3568_setup_overlay()
6511 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, in rk3568_setup_overlay()
6524 vop2_mask_write(vop2, RK3576_CLUSTER0_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3576_setup_win_dly()
6528 vop2_mask_write(vop2, RK3576_CLUSTER1_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3576_setup_win_dly()
6532 vop2_mask_write(vop2, RK3576_ESMART0_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6536 vop2_mask_write(vop2, RK3576_ESMART1_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6540 vop2_mask_write(vop2, RK3576_ESMART2_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6544 vop2_mask_write(vop2, RK3576_ESMART3_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6563 vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, LAYER_SEL_MASK, in rk3576_setup_overlay()