Lines Matching refs:vop2
1455 struct vop2 { struct
1473 static struct vop2 *rockchip_vop2; argument
1500 static inline bool is_vop3(struct vop2 *vop2) in is_vop3() argument
1502 if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3588) in is_vop3()
1636 struct vop2 *vop2 = cstate->private; in vop2_vp_find_attachable_win() local
1643 for (i = 0; i < vop2->data->nr_layers; i++) { in vop2_vp_find_attachable_win()
1644 if (vop2_win_can_attach_to_vp(&vop2->data->win_data[i], vp_id)) in vop2_vp_find_attachable_win()
1648 return vop2->data->win_data[i].phys_id; in vop2_vp_find_attachable_win()
1661 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) in vop2_writel() argument
1663 writel(v, vop2->regs + offset); in vop2_writel()
1664 vop2->regsbak[offset >> 2] = v; in vop2_writel()
1667 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) in vop2_readl() argument
1669 return readl(vop2->regs + offset); in vop2_readl()
1672 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, in vop2_mask_write() argument
1682 u32 cached_val = vop2->regsbak[offset >> 2]; in vop2_mask_write()
1685 vop2->regsbak[offset >> 2] = v; in vop2_mask_write()
1688 writel(v, vop2->regs + offset); in vop2_mask_write()
1691 static inline void vop2_grf_writel(struct vop2 *vop, void *grf_base, u32 offset, in vop2_grf_writel()
1700 static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, in vop2_grf_readl()
1845 static struct vop2_win_data *vop2_find_win_by_phys_id(struct vop2 *vop2, int phys_id) in vop2_find_win_by_phys_id() argument
1849 for (i = 0; i < vop2->data->nr_layers; i++) { in vop2_find_win_by_phys_id()
1850 if (vop2->data->win_data[i].phys_id == phys_id) in vop2_find_win_by_phys_id()
1851 return &vop2->data->win_data[i]; in vop2_find_win_by_phys_id()
1857 static struct vop2_power_domain_data *vop2_find_pd_data_by_id(struct vop2 *vop2, int pd_id) in vop2_find_pd_data_by_id() argument
1861 for (i = 0; i < vop2->data->nr_pd; i++) { in vop2_find_pd_data_by_id()
1862 if (vop2->data->pd[i].id == pd_id) in vop2_find_pd_data_by_id()
1863 return &vop2->data->pd[i]; in vop2_find_pd_data_by_id()
1869 static void rk3568_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3568_vop2_load_lut() argument
1875 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3568_vop2_load_lut()
1882 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3568_vop2_load_lut()
1886 static void rk3588_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3588_vop2_load_lut() argument
1892 if (vop2->version == VOP_VERSION_RK3576) in rk3588_vop2_load_lut()
1893 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3588_vop2_load_lut()
1897 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in rk3588_vop2_load_lut()
1904 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1906 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in rk3588_vop2_load_lut()
1910 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, in rockchip_vop2_gamma_lut_init() argument
1923 if (gamma_lut_en_num > vop2->data->nr_gammas) { in rockchip_vop2_gamma_lut_init()
1924 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); in rockchip_vop2_gamma_lut_init()
1960 if (vop2->version == VOP_VERSION_RK3568) { in rockchip_vop2_gamma_lut_init()
1961 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1965 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1968 rk3588_vop2_load_lut(vop2, cstate->splice_crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1980 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, in rockchip_vop2_cubic_lut_init() argument
2021 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, in rockchip_vop2_cubic_lut_init()
2023 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, in rockchip_vop2_cubic_lut_init()
2025 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
2027 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, in rockchip_vop2_cubic_lut_init()
2033 static void vop2_bcsh_reg_update(struct display_state *state, struct vop2 *vop2, in vop2_bcsh_reg_update() argument
2039 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, in vop2_bcsh_reg_update()
2041 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, in vop2_bcsh_reg_update()
2044 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, in vop2_bcsh_reg_update()
2046 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, in vop2_bcsh_reg_update()
2050 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
2055 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2058 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2060 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2063 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
2065 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, in vop2_bcsh_reg_update()
2067 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, in vop2_bcsh_reg_update()
2070 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, in vop2_bcsh_reg_update()
2074 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) in vop2_tv_config_update() argument
2137 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); in vop2_tv_config_update()
2139 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); in vop2_tv_config_update()
2142 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop2_setup_dly_for_vp() argument
2152 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; in vop2_setup_dly_for_vp()
2164 if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8) in vop2_setup_dly_for_vp()
2167 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, in vop2_setup_dly_for_vp()
2169 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop2_setup_dly_for_vp()
2172 static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop3_setup_pipe_dly() argument
2180 bg_dly = vop2->data->vp_data[crtc_id].win_dly + in vop3_setup_pipe_dly()
2181 vop2->data->vp_data[crtc_id].layer_mix_dly + in vop3_setup_pipe_dly()
2182 vop2->data->vp_data[crtc_id].hdr_mix_dly; in vop3_setup_pipe_dly()
2190 vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100, in vop3_setup_pipe_dly()
2192 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop3_setup_pipe_dly()
2195 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) in vop2_post_config() argument
2200 const struct vop2_data *vop2_data = vop2->data; in vop2_post_config()
2202 struct vop2_vp_plane_mask *plane_mask = &vop2->vp_plane_mask[cstate->crtc_id]; in vop2_post_config()
2219 if (vop2->version == VOP_VERSION_RK3576) { in vop2_post_config()
2239 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); in vop2_post_config()
2243 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); in vop2_post_config()
2246 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); in vop2_post_config()
2249 vop2_mask_write(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, in vop2_post_config()
2258 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); in vop2_post_config()
2261 if (is_vop3(vop2)) { in vop2_post_config()
2262 vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); in vop2_post_config()
2264 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); in vop2_post_config()
2267 plane_mask = &vop2->vp_plane_mask[cstate->splice_crtc_id]; in vop2_post_config()
2268 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); in vop2_post_config()
2274 static void vop3_post_acm_config(struct display_state *state, struct vop2 *vop2) in vop3_post_acm_config() argument
2287 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_acm_config()
2290 writel(0, vop2->regs + RK3528_ACM_CTRL); in vop3_post_acm_config()
2296 writel(1, vop2->regs + RK3528_ACM_FETCH_START); in vop3_post_acm_config()
2300 writel(value, vop2->regs + RK3528_ACM_CTRL); in vop3_post_acm_config()
2304 writel(value, vop2->regs + RK3528_ACM_DELTA_RANGE); in vop3_post_acm_config()
2312 writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2)); in vop3_post_acm_config()
2321 writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2)); in vop3_post_acm_config()
2330 writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2)); in vop3_post_acm_config()
2333 writel(1, vop2->regs + RK3528_ACM_FETCH_DONE); in vop3_post_acm_config()
2371 static void vop3_post_csc_config(struct display_state *state, struct vop2 *vop2) in vop3_post_csc_config() argument
2424 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2429 writel(value, vop2->regs + RK3528_VP0_CSC_COE01_02); in vop3_post_csc_config()
2432 writel(value, vop2->regs + RK3528_VP0_CSC_COE10_11); in vop3_post_csc_config()
2435 writel(value, vop2->regs + RK3528_VP0_CSC_COE12_20); in vop3_post_csc_config()
2438 writel(value, vop2->regs + RK3528_VP0_CSC_COE21_22); in vop3_post_csc_config()
2439 writel(csc_coef.csc_dc0, vop2->regs + RK3528_VP0_CSC_OFFSET0); in vop3_post_csc_config()
2440 writel(csc_coef.csc_dc1, vop2->regs + RK3528_VP0_CSC_OFFSET1); in vop3_post_csc_config()
2441 writel(csc_coef.csc_dc2, vop2->regs + RK3528_VP0_CSC_OFFSET2); in vop3_post_csc_config()
2445 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2449 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2451 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2453 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in vop3_post_csc_config()
2457 static void vop3_post_config(struct display_state *state, struct vop2 *vop2) in vop3_post_config() argument
2473 vop3_post_acm_config(state, vop2); in vop3_post_config()
2474 vop3_post_csc_config(state, vop2); in vop3_post_config()
2477 static int rk3576_vop2_wait_power_domain_on(struct vop2 *vop2, in rk3576_vop2_wait_power_domain_on() argument
2484 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3576_PMU_BISR_PDGEN_CON0, in rk3576_vop2_wait_power_domain_on()
2486 is_otp_bisr_en = vop2_grf_readl(vop2, vop2->grf, RK3576_SYS_GRF_MEMFAULT_STATUS0, in rk3576_vop2_wait_power_domain_on()
2489 return readl_poll_timeout(vop2->sys_pmu + RK3576_PMU_BISR_PWR_REPAIR_STATUS0, in rk3576_vop2_wait_power_domain_on()
2493 return readl_poll_timeout(vop2->sys_pmu + RK3576_PMU_PWR_GATE_STS, in rk3576_vop2_wait_power_domain_on()
2497 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3576_PMU_BISR_PDGEN_CON0, in rk3576_vop2_wait_power_domain_on()
2499 is_otp_bisr_en = vop2_grf_readl(vop2, vop2->grf, RK3576_SYS_GRF_MEMFAULT_STATUS0, in rk3576_vop2_wait_power_domain_on()
2502 return readl_poll_timeout(vop2->sys_pmu + RK3576_PMU_BISR_PWR_REPAIR_STATUS0, in rk3576_vop2_wait_power_domain_on()
2506 return readl_poll_timeout(vop2->sys_pmu + RK3576_PMU_PWR_GATE_STS, in rk3576_vop2_wait_power_domain_on()
2512 static int rk3576_vop2_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) in rk3576_vop2_power_domain_on() argument
2517 vop2_mask_write(vop2, RK3576_SYS_CLUSTER_PD_CTRL, EN_MASK, in rk3576_vop2_power_domain_on()
2520 vop2_mask_write(vop2, RK3576_SYS_ESMART_PD_CTRL, EN_MASK, in rk3576_vop2_power_domain_on()
2522 ret = rk3576_vop2_wait_power_domain_on(vop2, pd_data); in rk3576_vop2_power_domain_on()
2531 static int rk3588_vop2_wait_power_domain_on(struct vop2 *vop2, in rk3588_vop2_wait_power_domain_on() argument
2549 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); in rk3588_vop2_wait_power_domain_on()
2553 return readl_poll_timeout(vop2->sys_pmu + RK3588_PMU_BISR_STATUS5, val, in rk3588_vop2_wait_power_domain_on()
2558 return readl_poll_timeout(vop2->regs + RK3568_SYS_STATUS0, val, in rk3588_vop2_wait_power_domain_on()
2563 static int rk3588_vop2_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) in rk3588_vop2_power_domain_on() argument
2567 vop2_mask_write(vop2, RK3588_SYS_PD_CTRL, EN_MASK, in rk3588_vop2_power_domain_on()
2569 ret = rk3588_vop2_wait_power_domain_on(vop2, pd_data); in rk3588_vop2_power_domain_on()
2578 static int vop2_power_domain_on(struct vop2 *vop2, int pd_id) in vop2_power_domain_on() argument
2586 pd_data = vop2_find_pd_data_by_id(vop2, pd_id); in vop2_power_domain_on()
2593 ret = vop2_power_domain_on(vop2, pd_data->parent_id); in vop2_power_domain_on()
2606 if (vop2->version == VOP_VERSION_RK3576) in vop2_power_domain_on()
2607 ret = rk3576_vop2_power_domain_on(vop2, pd_data); in vop2_power_domain_on()
2609 ret = rk3588_vop2_power_domain_on(vop2, pd_data); in vop2_power_domain_on()
2614 static void rk3588_vop2_regsbak(struct vop2 *vop2) in rk3588_vop2_regsbak() argument
2616 u32 *base = vop2->regs; in rk3588_vop2_regsbak()
2622 for (i = 0; i < (vop2->reg_len >> 2); i++) in rk3588_vop2_regsbak()
2623 vop2->regsbak[i] = base[i]; in rk3588_vop2_regsbak()
2626 static bool vop3_ignore_plane(struct vop2 *vop2, struct vop2_win_data *win) in vop3_ignore_plane() argument
2628 if (!is_vop3(vop2)) in vop3_ignore_plane()
2631 if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE && in vop3_ignore_plane()
2634 else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE && in vop3_ignore_plane()
2637 else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE && in vop3_ignore_plane()
2640 else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_4K_MODE && in vop3_ignore_plane()
2647 static void vop3_init_esmart_scale_engine(struct vop2 *vop2) in vop3_init_esmart_scale_engine() argument
2654 for (i = 0; i < vop2->data->nr_layers; i++) { in vop3_init_esmart_scale_engine()
2655 win_data = &vop2->data->win_data[i]; in vop3_init_esmart_scale_engine()
2656 if (win_data->type == CLUSTER_LAYER || vop3_ignore_plane(vop2, win_data)) in vop3_init_esmart_scale_engine()
2663 static int vop3_get_esmart_lb_mode(struct vop2 *vop2) in vop3_get_esmart_lb_mode() argument
2665 const struct vop2_esmart_lb_map *esmart_lb_mode_map = vop2->data->esmart_lb_mode_map; in vop3_get_esmart_lb_mode()
2669 return vop2->esmart_lb_mode; in vop3_get_esmart_lb_mode()
2671 for (i = 0; i < vop2->data->esmart_lb_mode_num; i++) { in vop3_get_esmart_lb_mode()
2672 if (vop2->esmart_lb_mode == esmart_lb_mode_map->lb_mode) in vop3_get_esmart_lb_mode()
2677 if (i == vop2->data->esmart_lb_mode_num) in vop3_get_esmart_lb_mode()
2678 printf("Unsupported esmart_lb_mode:%d\n", vop2->esmart_lb_mode); in vop3_get_esmart_lb_mode()
2680 return vop2->data->esmart_lb_mode_map[0].lb_map_value; in vop3_get_esmart_lb_mode()
2686 struct vop2 *vop2 = cstate->private; in vop2_plane_mask_to_possible_vp_mask() local
2687 const struct vop2_data *vop2_data = vop2->data; in vop2_plane_mask_to_possible_vp_mask()
2705 win_data = vop2_find_win_by_phys_id(vop2, phys_id); in vop2_plane_mask_to_possible_vp_mask()
2719 struct vop2 *vop2 = cstate->private; in vop2_plane_mask_check() local
2732 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_plane_mask_check()
2775 win_data = vop2_find_win_by_phys_id(vop2, phys_id); in vop2_plane_mask_check()
2798 if (assigned_plane_mask != vop2->data->plane_mask_base) { in vop2_plane_mask_check()
2800 vop2->data->plane_mask_base, assigned_plane_mask); in vop2_plane_mask_check()
2816 struct vop2 *vop2 = cstate->private; in rockchip_cursor_plane_assign() local
2821 win_data = vop2_find_win_by_phys_id(vop2, cstate->crtc->vps[vp_id].cursor_plane_id); in rockchip_cursor_plane_assign()
2824 vop2->vp_plane_mask[vp_id].cursor_plane_id = in rockchip_cursor_plane_assign()
2830 for (i = 0; i < vop2->data->nr_layers; i++) { in rockchip_cursor_plane_assign()
2831 win_data = &vop2->data->win_data[i]; in rockchip_cursor_plane_assign()
2839 for (j = 0; j < vop2->data->nr_vps; j++) { in rockchip_cursor_plane_assign()
2840 if (win_data->phys_id == vop2->vp_plane_mask[j].cursor_plane_id) in rockchip_cursor_plane_assign()
2845 if (j < vop2->data->nr_vps) in rockchip_cursor_plane_assign()
2848 vop2->vp_plane_mask[vp_id].cursor_plane_id = win_data->phys_id; in rockchip_cursor_plane_assign()
2852 vop2->vp_plane_mask[vp_id].cursor_plane_id = ROCKCHIP_VOP2_PHY_ID_INVALID; in rockchip_cursor_plane_assign()
2865 struct vop2 *vop2 = cstate->private; in rk3528_assign_plane_mask() local
2872 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3528_assign_plane_mask()
2876 for (j = 0; j < vop2->data->nr_layers; j++) { in rk3528_assign_plane_mask()
2877 win_data = &vop2->data->win_data[j]; in rk3528_assign_plane_mask()
2885 for (k = 0; k < vop2->data->nr_vps; k++) { in rk3528_assign_plane_mask()
2886 if (win_data->phys_id == vop2->vp_plane_mask[k].primary_plane_id) in rk3528_assign_plane_mask()
2891 if (k < vop2->data->nr_vps) in rk3528_assign_plane_mask()
2894 vop2->vp_plane_mask[i].attached_layers_nr = 1; in rk3528_assign_plane_mask()
2895 vop2->vp_plane_mask[i].primary_plane_id = win_data->phys_id; in rk3528_assign_plane_mask()
2896 vop2->vp_plane_mask[i].attached_layers[0] = win_data->phys_id; in rk3528_assign_plane_mask()
2897 vop2->vp_plane_mask[i].plane_mask |= BIT(win_data->phys_id); in rk3528_assign_plane_mask()
2902 if (vop2->vp_plane_mask[i].primary_plane_id == ROCKCHIP_VOP2_PHY_ID_INVALID) in rk3528_assign_plane_mask()
2913 struct vop2 *vop2 = cstate->private; in rk3568_assign_plane_mask() local
2923 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_assign_plane_mask()
2932 plane_mask = vop2->data->plane_mask; in rk3568_assign_plane_mask()
2942 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_assign_plane_mask()
2945 vop2->vp_plane_mask[i] = plane_mask[0]; in rk3568_assign_plane_mask()
2954 vop2->vp_plane_mask[0] = plane_mask[0]; in rk3568_assign_plane_mask()
2968 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_assign_plane_mask()
2972 vop2->vp_plane_mask[i] = plane_mask[j++]; in rk3568_assign_plane_mask()
2982 if (vop2->version == VOP_VERSION_RK3588 && active_vp_num == 1) in rk3568_assign_plane_mask()
2983 vop2->vp_plane_mask[(i + 1) % vop2->data->nr_vps] = plane_mask[j++]; in rk3568_assign_plane_mask()
2987 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_assign_plane_mask()
2988 nr_planes = vop2->vp_plane_mask[i].attached_layers_nr; in rk3568_assign_plane_mask()
2990 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in rk3568_assign_plane_mask()
2991 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); in rk3568_assign_plane_mask()
3001 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_assign_plane_mask()
3002 vop2->vp_plane_mask[i].cursor_plane_id = ROCKCHIP_VOP2_PHY_ID_INVALID; in rk3568_assign_plane_mask()
3008 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) in vop2_global_initial() argument
3011 const struct vop2_data *vop2_data = vop2->data; in vop2_global_initial()
3020 if (vop2->global_init) in vop2_global_initial()
3027 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
3028 vp_plane_mask = &vop2->vp_plane_mask[i]; in vop2_global_initial()
3039 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, in vop2_global_initial()
3046 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
3049 vop2->vp_plane_mask[i].attached_layers_nr = nr_planes; in vop2_global_initial()
3058 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; in vop2_global_initial()
3059 vop2->vp_plane_mask[i].plane_mask = plane_mask; in vop2_global_initial()
3063 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; in vop2_global_initial()
3064 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); in vop2_global_initial()
3078 if (vop2->version == VOP_VERSION_RK3588) in vop2_global_initial()
3079 rk3588_vop2_regsbak(vop2); in vop2_global_initial()
3081 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); in vop2_global_initial()
3083 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, in vop2_global_initial()
3085 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in vop2_global_initial()
3088 for (i = 0; i < vop2->data->nr_vps; i++) { in vop2_global_initial()
3089 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); in vop2_global_initial()
3090 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) in vop2_global_initial()
3092 vop2_plane_phys_id_to_string(vop2->vp_plane_mask[i].attached_layers[j])); in vop2_global_initial()
3094 vop2_plane_phys_id_to_string(vop2->vp_plane_mask[i].primary_plane_id)); in vop2_global_initial()
3099 if (is_vop3(vop2)) { in vop2_global_initial()
3114 vop2->esmart_lb_mode = *tmp; in vop2_global_initial()
3116 vop2->esmart_lb_mode = vop2->data->esmart_lb_mode; in vop2_global_initial()
3117 if (vop2->version == VOP_VERSION_RK3576) in vop2_global_initial()
3118 vop2_mask_write(vop2, RK3576_SYS_ESMART_PD_CTRL, in vop2_global_initial()
3121 vop3_get_esmart_lb_mode(vop2), true); in vop2_global_initial()
3123 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, in vop2_global_initial()
3126 vop3_get_esmart_lb_mode(vop2), false); in vop2_global_initial()
3128 vop3_init_esmart_scale_engine(vop2); in vop2_global_initial()
3130 if (vop2->version == VOP_VERSION_RK3576) in vop2_global_initial()
3131 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, in vop2_global_initial()
3134 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK, in vop2_global_initial()
3148 if (vop2->version == VOP_VERSION_RK3528 || vop2->version == VOP_VERSION_RK3562 || in vop2_global_initial()
3149 vop2->version == VOP_VERSION_RK3576) in vop2_global_initial()
3150 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in vop2_global_initial()
3154 if (vop2->version == VOP_VERSION_RK3568) in vop2_global_initial()
3155 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); in vop2_global_initial()
3157 if (vop2->version == VOP_VERSION_RK3576) { in vop2_global_initial()
3158 vop2->merge_irq = ofnode_read_bool(cstate->node, "rockchip,vop-merge-irq"); in vop2_global_initial()
3161 vop2_mask_write(vop2, RK3576_SYS_MMU_CTRL, EN_MASK, RKMMU_V2_EN_SHIFT, 1, true); in vop2_global_initial()
3164 vop2_writel(vop2, 0xca0, 0xc8); in vop2_global_initial()
3165 vop2_writel(vop2, 0xca4, 0x01000100); in vop2_global_initial()
3166 vop2_writel(vop2, 0xca8, 0x03ff0100); in vop2_global_initial()
3167 vop2_writel(vop2, 0xda0, 0xc8); in vop2_global_initial()
3168 vop2_writel(vop2, 0xda4, 0x01000100); in vop2_global_initial()
3169 vop2_writel(vop2, 0xda8, 0x03ff0100); in vop2_global_initial()
3171 if (vop2->version == VOP_VERSION_RK3576 && vop2->merge_irq == true) in vop2_global_initial()
3172 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, in vop2_global_initial()
3176 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, INTERLACE_FRM_REG_DONE_MASK, in vop2_global_initial()
3180 vop2->global_init = true; in vop2_global_initial()
3183 static void rockchip_vop2_sharp_init(struct vop2 *vop2, struct display_state *state) in rockchip_vop2_sharp_init() argument
3186 const struct vop2_data *vop2_data = vop2->data; in rockchip_vop2_sharp_init()
3200 vop2->sharp_res = (void *)sharp_regs.start; in rockchip_vop2_sharp_init()
3206 writel(true << SW_SHARP_ENABLE_SHIFT, vop2->sharp_res + RK3576_SHARP_CTRL); in rockchip_vop2_sharp_init()
3209 static void rockchip_vop2_acm_init(struct vop2 *vop2, struct display_state *state) in rockchip_vop2_acm_init() argument
3212 const struct vop2_data *vop2_data = vop2->data; in rockchip_vop2_acm_init()
3234 vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset, in rockchip_vop2_acm_init()
3310 static void rockchip_vop2_of_get_dsp_lut(struct vop2 *vop2, struct display_state *state) in rockchip_vop2_of_get_dsp_lut() argument
3330 static int vop2_initial(struct vop2 *vop2, struct display_state *state) in vop2_initial() argument
3332 rockchip_vop2_of_get_dsp_lut(vop2, state); in vop2_initial()
3334 rockchip_vop2_gamma_lut_init(vop2, state); in vop2_initial()
3335 rockchip_vop2_cubic_lut_init(vop2, state); in vop2_initial()
3336 rockchip_vop2_sharp_init(vop2, state); in vop2_initial()
3337 rockchip_vop2_acm_init(vop2, state); in vop2_initial()
3359 rockchip_vop2 = calloc(1, sizeof(struct vop2)); in rockchip_vop2_preinit()
3362 memset(rockchip_vop2, 0, sizeof(struct vop2)); in rockchip_vop2_preinit()
3479 struct vop2 *vop2 = cstate->private; in vop2_calc_cru_cfg() local
3520 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3524 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, if_pixclk_rate); in vop2_calc_cru_cfg()
3548 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3551 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, dclk_core_rate); in vop2_calc_cru_cfg()
3568 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3571 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, dclk_rate); in vop2_calc_cru_cfg()
3641 struct vop2 *vop2 = cstate->private; in rk3588_vop2_if_cfg() local
3663 if (!vop2->data->nr_dscs) { in rk3588_vop2_if_cfg()
3684 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
3686 vop2_grf_writel(vop2, vop2->grf, RK3588_GRF_SOC_CON1, EN_MASK, in rk3588_vop2_if_cfg()
3691 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
3693 vop2_grf_writel(vop2, vop2->grf, RK3588_GRF_SOC_CON1, EN_MASK, in rk3588_vop2_if_cfg()
3696 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, RK3588_BT1120_YC_SWAP_SHIFT, in rk3588_vop2_if_cfg()
3701 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, in rk3588_vop2_if_cfg()
3703 vop2_grf_writel(vop2, vop2->grf, RK3588_GRF_SOC_CON1, EN_MASK, in rk3588_vop2_if_cfg()
3706 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, RK3588_BT656_YC_SWAP_SHIFT, in rk3588_vop2_if_cfg()
3717 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3720 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, in rk3588_vop2_if_cfg()
3722 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); in rk3588_vop2_if_cfg()
3723 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3727 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3729 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3742 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3745 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, in rk3588_vop2_if_cfg()
3747 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3749 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3753 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3755 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3761 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3588_vop2_if_cfg()
3764 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3588_vop2_if_cfg()
3769 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3773 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3777 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3781 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3790 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, in rk3588_vop2_if_cfg()
3792 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
3794 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3797 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3800 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3805 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, in rk3588_vop2_if_cfg()
3807 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3809 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3812 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3815 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3820 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, in rk3588_vop2_if_cfg()
3822 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
3824 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3827 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3831 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3834 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3836 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, in rk3588_vop2_if_cfg()
3842 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, in rk3588_vop2_if_cfg()
3844 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3846 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3849 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, in rk3588_vop2_if_cfg()
3853 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3856 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3858 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, in rk3588_vop2_if_cfg()
3864 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, in rk3588_vop2_if_cfg()
3866 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, in rk3588_vop2_if_cfg()
3871 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, in rk3588_vop2_if_cfg()
3873 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, in rk3588_vop2_if_cfg()
3877 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
3879 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, in rk3588_vop2_if_cfg()
3890 struct vop2 *vop2 = cstate->private; in rk3576_vop2_if_cfg() local
3892 u8 port_pix_rate = vop2->data->vp_data[cstate->crtc_id].pixel_rate; in rk3576_vop2_if_cfg()
3915 if (vop2->data->vp_data[cstate->crtc_id].feature & VOP_FEATURE_POST_SHARP) in rk3576_vop2_if_cfg()
3917 vop2->sharp_res + RK3576_SHARP_CTRL); in rk3576_vop2_if_cfg()
3965 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3968 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3973 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
3976 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3978 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3980 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3982 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
3984 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
3986 vop2_grf_writel(vop2, vop2->ioc_grf, RK3576_VCCIO_IOC_MISC_CON8, EN_MASK, in rk3576_vop2_if_cfg()
3992 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
3995 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3997 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3999 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4001 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4003 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4005 vop2_grf_writel(vop2, vop2->ioc_grf, RK3576_VCCIO_IOC_MISC_CON8, EN_MASK, in rk3576_vop2_if_cfg()
4008 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4014 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4017 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4019 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4021 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4023 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4025 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4027 vop2_grf_writel(vop2, vop2->ioc_grf, RK3576_VCCIO_IOC_MISC_CON8, EN_MASK, in rk3576_vop2_if_cfg()
4030 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4035 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4038 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4041 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4043 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4045 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4047 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4053 if (vop2->version == VOP_VERSION_RK3576) in rk3576_vop2_if_cfg()
4055 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4059 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4063 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4065 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4071 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4074 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4078 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4082 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4086 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4090 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4099 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4102 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4105 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4107 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4109 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4111 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4113 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4118 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4121 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4124 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4126 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4128 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4130 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4132 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4137 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4140 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4143 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4145 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4147 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4149 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4154 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4157 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4160 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4162 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4164 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4166 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4171 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_DCLK_SEL_MASK, in rk3576_vop2_if_cfg()
4174 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PIX_CLK_SEL_MASK, in rk3576_vop2_if_cfg()
4177 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4179 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4181 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PORT_SEL_MASK, in rk3576_vop2_if_cfg()
4183 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, RK3576_IF_PIN_POL_MASK, in rk3576_vop2_if_cfg()
4194 struct vop2 *vop2 = cstate->private; in rk3568_vop2_setup_dual_channel_if() local
4199 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4201 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4204 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4210 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4213 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4218 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4220 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4230 struct vop2 *vop2 = cstate->private; in rk3568_vop2_if_cfg() local
4239 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
4241 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4243 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4245 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
4250 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
4252 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, in rk3568_vop2_if_cfg()
4254 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4256 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
4261 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3568_vop2_if_cfg()
4263 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4265 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
4270 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3568_vop2_if_cfg()
4272 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4274 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4276 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4281 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, in rk3568_vop2_if_cfg()
4283 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4285 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4287 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4293 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3568_vop2_if_cfg()
4295 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4297 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4299 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_MIPI_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4304 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, in rk3568_vop2_if_cfg()
4306 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4308 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4310 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_MIPI_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4321 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, in rk3568_vop2_if_cfg()
4323 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4325 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4327 vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_EDP_PIN_POL_MASK, in rk3568_vop2_if_cfg()
4332 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3568_vop2_if_cfg()
4334 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3568_vop2_if_cfg()
4336 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4338 vop2_mask_write(vop2, RK3568_DSP_IF_POL, in rk3568_vop2_if_cfg()
4351 struct vop2 *vop2 = cstate->private; in rk3562_vop2_if_cfg() local
4361 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3562_vop2_if_cfg()
4363 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
4365 vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK, in rk3562_vop2_if_cfg()
4367 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
4372 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3562_vop2_if_cfg()
4374 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
4376 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
4378 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
4383 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3562_vop2_if_cfg()
4385 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3562_vop2_if_cfg()
4387 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
4389 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK, in rk3562_vop2_if_cfg()
4393 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3562_vop2_if_cfg()
4395 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rk3562_vop2_if_cfg()
4408 struct vop2 *vop2 = cstate->private; in rk3528_vop2_if_cfg() local
4415 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3528_vop2_if_cfg()
4417 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3528_vop2_if_cfg()
4422 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3528_vop2_if_cfg()
4424 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, in rk3528_vop2_if_cfg()
4426 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3528_vop2_if_cfg()
4428 vop2_mask_write(vop2, RK3568_DSP_IF_POL, in rk3528_vop2_if_cfg()
4440 struct vop2 *vop2 = cstate->private; in vop2_post_color_swap() local
4448 if ((vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3576)) { in vop2_post_color_swap()
4456 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, in vop2_post_color_swap()
4500 static void vop2_load_pps(struct display_state *state, struct vop2 *vop2, u8 dsc_id) in vop2_load_pps() argument
4505 const struct vop2_data *vop2_data = vop2->data; in vop2_load_pps()
4529 vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); in vop2_load_pps()
4532 static void vop2_dsc_enable(struct display_state *state, struct vop2 *vop2, u8 dsc_id, u64 dclk_rat… in vop2_dsc_enable() argument
4538 const struct vop2_data *vop2_data = vop2->data; in vop2_dsc_enable()
4558 if (!vop2->data->nr_dscs) { in vop2_dsc_enable()
4568 if (vop2_power_domain_on(vop2, dsc_data->pd_id)) in vop2_dsc_enable()
4572 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
4574 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, in vop2_dsc_enable()
4587 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, in vop2_dsc_enable()
4590 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, in vop2_dsc_enable()
4595 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, in vop2_dsc_enable()
4597 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, in vop2_dsc_enable()
4599 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, in vop2_dsc_enable()
4601 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, in vop2_dsc_enable()
4603 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, in vop2_dsc_enable()
4605 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
4607 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, in vop2_dsc_enable()
4659 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, in vop2_dsc_enable()
4661 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, in vop2_dsc_enable()
4677 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, in vop2_dsc_enable()
4683 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, in vop2_dsc_enable()
4686 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, in vop2_dsc_enable()
4688 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, in vop2_dsc_enable()
4692 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, in vop2_dsc_enable()
4698 vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val); in vop2_dsc_enable()
4700 vop2_load_pps(state, vop2, dsc_id); in vop2_dsc_enable()
4703 vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val); in vop2_dsc_enable()
4715 struct vop2 *vop2 = cstate->private; in is_extend_pll() local
4721 if (vop2->version != VOP_VERSION_RK3588 && vop2->version != VOP_VERSION_RK3576) in is_extend_pll()
4755 struct vop2 *vop2 = cstate->private; in vop3_mcu_mode_setup() local
4758 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4760 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4762 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_mode_setup()
4764 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_mode_setup()
4766 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_mode_setup()
4768 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_mode_setup()
4770 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_mode_setup()
4777 struct vop2 *vop2 = cstate->private; in vop3_mcu_bypass_mode_setup() local
4780 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4782 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4784 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_bypass_mode_setup()
4786 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_bypass_mode_setup()
4788 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_bypass_mode_setup()
4790 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_bypass_mode_setup()
4792 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_bypass_mode_setup()
4801 struct vop2 *vop2 = cstate->private; in rockchip_vop2_send_mcu_cmd() local
4815 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4817 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
4820 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4824 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4826 vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset, in rockchip_vop2_send_mcu_cmd()
4831 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4850 static void vop2_dither_setup(struct vop2 *vop2, int bus_format, int crtc_id) in vop2_dither_setup() argument
4852 const struct vop2_data *vop2_data = vop2->data; in vop2_dither_setup()
4860 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4862 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4870 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4872 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4887 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4897 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4907 if (vop2->version == VOP_VERSION_RK3576) { in vop2_dither_setup()
4908 vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_0 + vp_offset, 0x00000000); in vop2_dither_setup()
4909 vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_1 + vp_offset, 0x01000100); in vop2_dither_setup()
4910 vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_2 + vp_offset, 0x04030100); in vop2_dither_setup()
4913 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4916 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4918 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, DITHER_DOWN_SEL_MASK, in vop2_dither_setup()
4921 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4923 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, DITHER_DOWN_SEL_MASK, in vop2_dither_setup()
4934 struct vop2 *vop2 = cstate->private; in rockchip_vop2_init() local
4972 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; in rockchip_vop2_init()
4979 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, in rockchip_vop2_init()
4983 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
4985 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
4988 if (vop2->data->vp_data[cstate->crtc_id].urgency) { in rockchip_vop2_init()
4989 u8 urgen_thl = vop2->data->vp_data[cstate->crtc_id].urgency->urgen_thl; in rockchip_vop2_init()
4990 u8 urgen_thh = vop2->data->vp_data[cstate->crtc_id].urgency->urgen_thh; in rockchip_vop2_init()
4992 vop2_mask_write(vop2, RK3576_SYS_AXI_HURRY_CTRL0_IMD, EN_MASK, in rockchip_vop2_init()
4994 vop2_mask_write(vop2, RK3576_SYS_AXI_HURRY_CTRL1_IMD, EN_MASK, in rockchip_vop2_init()
4996 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
4998 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, POST_URGENCY_THL_MASK, in rockchip_vop2_init()
5000 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, POST_URGENCY_THH_MASK, in rockchip_vop2_init()
5004 vop2_initial(vop2, state); in rockchip_vop2_init()
5005 if (vop2->version == VOP_VERSION_RK3588) in rockchip_vop2_init()
5007 else if (vop2->version == VOP_VERSION_RK3576) in rockchip_vop2_init()
5009 else if (vop2->version == VOP_VERSION_RK3568) in rockchip_vop2_init()
5011 else if (vop2->version == VOP_VERSION_RK3562) in rockchip_vop2_init()
5013 else if (vop2->version == VOP_VERSION_RK3528) in rockchip_vop2_init()
5022 if (vop2->version == VOP_VERSION_RK3588 && in rockchip_vop2_init()
5026 if (vop2->version == VOP_VERSION_RK3576 && in rockchip_vop2_init()
5029 else if (vop2->version == VOP_VERSION_RK3588 && in rockchip_vop2_init()
5032 else if (vop2->version == VOP_VERSION_RK3576 && in rockchip_vop2_init()
5041 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, in rockchip_vop2_init()
5044 vop2_dither_setup(vop2, conn_state->bus_format, cstate->crtc_id); in rockchip_vop2_init()
5046 vop2_dither_setup(vop2, conn_state->bus_format, cstate->splice_crtc_id); in rockchip_vop2_init()
5049 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
5054 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, in rockchip_vop2_init()
5058 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); in rockchip_vop2_init()
5061 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); in rockchip_vop2_init()
5067 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, in rockchip_vop2_init()
5071 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); in rockchip_vop2_init()
5072 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5074 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5076 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5081 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5083 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5087 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, in rockchip_vop2_init()
5090 if (vop2->version == VOP_VERSION_RK3528 || in rockchip_vop2_init()
5091 vop2->version == VOP_VERSION_RK3562 || in rockchip_vop2_init()
5092 vop2->version == VOP_VERSION_RK3568) { in rockchip_vop2_init()
5095 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5098 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5102 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
5105 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_init()
5109 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, in rockchip_vop2_init()
5116 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); in rockchip_vop2_init()
5118 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, in rockchip_vop2_init()
5121 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); in rockchip_vop2_init()
5124 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5128 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5131 vop2_tv_config_update(state, vop2); in rockchip_vop2_init()
5132 vop2_post_config(state, vop2); in rockchip_vop2_init()
5134 vop3_post_config(state, vop2); in rockchip_vop2_init()
5138 vop2_dsc_enable(state, vop2, 0, dclk_rate * 1000LL); in rockchip_vop2_init()
5139 vop2_dsc_enable(state, vop2, 1, dclk_rate * 1000LL); in rockchip_vop2_init()
5141 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL); in rockchip_vop2_init()
5168 if (vop2->version == VOP_VERSION_RK3528) { in rockchip_vop2_init()
5184 if (vop2->version == VOP_VERSION_RK3576) in rockchip_vop2_init()
5212 if (vop2->version == VOP_VERSION_RK3528) { in rockchip_vop2_init()
5244 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, in rockchip_vop2_init()
5246 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, in rockchip_vop2_init()
5250 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_init()
5251 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5259 static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win_data *win, in vop2_setup_scale() argument
5272 if (is_vop3(vop2)) { in vop2_setup_scale()
5273 if (vop2->version == VOP_VERSION_RK3576 && win->type == CLUSTER_LAYER) { in vop2_setup_scale()
5300 if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) { in vop2_setup_scale()
5345 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1) && !is_vop3(vop2)) { in vop2_setup_scale()
5350 if (is_vop3(vop2)) { in vop2_setup_scale()
5359 if (vop2->version == VOP_VERSION_RK3576) { in vop2_setup_scale()
5369 vop2_writel(vop2, RK3576_CLUSTER0_WIN0_ZME_DERING_PARA + win_offset, in vop2_setup_scale()
5371 vop2_mask_write(vop2, RK3576_CLUSTER0_WIN0_ZME_CTRL + win_offset, in vop2_setup_scale()
5380 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset, in vop2_setup_scale()
5383 if (is_vop3(vop2)) { in vop2_setup_scale()
5384 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5386 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5388 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5391 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5394 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5398 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5401 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5406 if (!is_vop3(vop2) || win->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) { in vop2_setup_scale()
5407 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5409 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5411 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5413 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5416 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5418 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5420 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5422 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, in vop2_setup_scale()
5426 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, in vop2_setup_scale()
5429 if (is_vop3(vop2)) { in vop2_setup_scale()
5430 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5432 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5434 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5438 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5440 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_setup_scale()
5443 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5445 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5448 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5451 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, in vop2_setup_scale()
5457 static void vop2_axi_config(struct vop2 *vop2, struct vop2_win_data *win) in vop2_axi_config() argument
5462 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, in vop2_axi_config()
5464 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, in vop2_axi_config()
5466 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, in vop2_axi_config()
5469 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, in vop2_axi_config()
5471 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, in vop2_axi_config()
5473 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, in vop2_axi_config()
5498 struct vop2 *vop2 = cstate->private; in vop2_set_cluster_win() local
5499 const struct vop2_data *vop2_data = vop2->data; in vop2_set_cluster_win()
5543 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); in vop2_set_cluster_win()
5545 if (vop2->version != VOP_VERSION_RK3568) in vop2_set_cluster_win()
5546 vop2_axi_config(vop2, win); in vop2_set_cluster_win()
5551 if (is_vop3(vop2)) { in vop2_set_cluster_win()
5552 vop2_mask_write(vop2, RK3576_CLUSTER0_PORT_SEL + win_offset, in vop2_set_cluster_win()
5561 if (vop2->version >= VOP_VERSION_RK3588) in vop2_set_cluster_win()
5562 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset, in vop2_set_cluster_win()
5565 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, in vop2_set_cluster_win()
5568 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, in vop2_set_cluster_win()
5570 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir); in vop2_set_cluster_win()
5571 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset, in vop2_set_cluster_win()
5574 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info); in vop2_set_cluster_win()
5575 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info); in vop2_set_cluster_win()
5576 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st); in vop2_set_cluster_win()
5580 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
5583 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, in vop2_set_cluster_win()
5587 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
5590 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); in vop2_set_cluster_win()
5591 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); in vop2_set_cluster_win()
5601 struct vop2 *vop2 = cstate->private; in vop2_set_smart_win() local
5602 const struct vop2_data *vop2_data = vop2->data; in vop2_set_smart_win()
5622 struct vop2_win_data *source_win = vop2_find_win_by_phys_id(vop2, win->source_win_id); in vop2_set_smart_win()
5629 val = vop2_readl(vop2, RK3568_ESMART0_REGION0_CTRL + source_win->reg_offset); in vop2_set_smart_win()
5671 if (is_vop3(vop2)) { in vop2_set_smart_win()
5672 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, in vop2_set_smart_win()
5675 vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset, in vop2_set_smart_win()
5681 if (vop2->version == VOP_VERSION_RK3576 && cstate->crtc_id == 0 && in vop2_set_smart_win()
5684 vop2_mask_write(vop2, RK3576_ESMART0_PORT_SEL + win_offset, in vop2_set_smart_win()
5689 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); in vop2_set_smart_win()
5691 if (vop2->version != VOP_VERSION_RK3568) in vop2_set_smart_win()
5692 vop2_axi_config(vop2, win); in vop2_set_smart_win()
5696 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, in vop2_set_smart_win()
5699 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_set_smart_win()
5703 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, in vop2_set_smart_win()
5706 if (vop2->version == VOP_VERSION_RK3576) in vop2_set_smart_win()
5707 vop2_writel(vop2, RK3576_ESMART0_ALPHA_MAP + win_offset, 0x8000ff00); in vop2_set_smart_win()
5709 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); in vop2_set_smart_win()
5710 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, in vop2_set_smart_win()
5713 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, in vop2_set_smart_win()
5715 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, in vop2_set_smart_win()
5717 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); in vop2_set_smart_win()
5721 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, in vop2_set_smart_win()
5724 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, in vop2_set_smart_win()
5728 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
5731 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
5785 struct vop2 *vop2 = cstate->private; in rockchip_vop2_set_plane() local
5788 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_set_plane()
5797 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); in rockchip_vop2_set_plane()
5804 if (vop3_ignore_plane(vop2, win_data)) in rockchip_vop2_set_plane()
5807 if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3576) { in rockchip_vop2_set_plane()
5808 if (vop2_power_domain_on(vop2, win_data->pd_id)) in rockchip_vop2_set_plane()
5814 splice_win_data = vop2_find_win_by_phys_id(vop2, win_data->splice_win_id); in rockchip_vop2_set_plane()
5817 if (vop2_power_domain_on(vop2, splice_win_data->pd_id)) in rockchip_vop2_set_plane()
5857 struct vop2 *vop2 = cstate->private; in vop2_dsc_cfg_done() local
5862 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, in vop2_dsc_cfg_done()
5864 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, in vop2_dsc_cfg_done()
5867 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, in vop2_dsc_cfg_done()
5875 struct vop2 *vop2 = cstate->private; in rockchip_vop2_enable() local
5879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5885 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_enable()
5891 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5901 struct vop2 *vop2 = cstate->private; in rk3588_vop2_post_enable() local
5907 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, in rk3588_vop2_post_enable()
5911 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, in rk3588_vop2_post_enable()
5915 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rk3588_vop2_post_enable()
5916 ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val, in rk3588_vop2_post_enable()
5935 struct vop2 *vop2 = cstate->private; in rk3576_vop2_post_enable() local
5941 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5945 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5949 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5953 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rk3576_vop2_post_enable()
5954 ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val, in rk3576_vop2_post_enable()
5972 struct vop2 *vop2 = cstate->private; in rockchip_vop2_post_enable() local
5974 if (vop2->version == VOP_VERSION_RK3588) in rockchip_vop2_post_enable()
5976 else if (vop2->version == VOP_VERSION_RK3576) in rockchip_vop2_post_enable()
5985 struct vop2 *vop2 = cstate->private; in rockchip_vop2_disable() local
5989 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_disable()
5995 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_disable()
6003 struct vop2 *vop2 = cstate->private; in rockchip_vop2_fixup_dts() local
6018 if (vop_fix_dts || is_vop3(vop2)) in rockchip_vop2_fixup_dts()
6023 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; in rockchip_vop2_fixup_dts()
6030 vop2->vp_plane_mask[vp_id].primary_plane_id, in rockchip_vop2_fixup_dts()
6031 vop2->vp_plane_mask[vp_id].cursor_plane_id); in rockchip_vop2_fixup_dts()
6036 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); in rockchip_vop2_fixup_dts()
6037 if (vop2->vp_plane_mask[vp_id].cursor_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) in rockchip_vop2_fixup_dts()
6039 vop2->vp_plane_mask[vp_id].cursor_plane_id, 1); in rockchip_vop2_fixup_dts()
6091 struct vop2 *vop2 = cstate->private; in rockchip_vop2_mode_fixup() local
6106 if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3588) { in rockchip_vop2_mode_fixup()
6140 if (vop2->version == VOP_VERSION_RK3588) { in rockchip_vop2_mode_fixup()
6155 if (vop2->version == VOP_VERSION_RK3576) { in rockchip_vop2_mode_fixup()
6186 if (vop2->version == VOP_VERSION_RK3528 && conn_state->output_if & VOP_OUTPUT_IF_BT656) in rockchip_vop2_mode_fixup()
6201 struct vop2 *vop2 = cstate->private; in rockchip_vop2_plane_check() local
6207 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_plane_check()
6209 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); in rockchip_vop2_plane_check()
6232 struct vop2 *vop2 = cstate->private; in rockchip_vop2_apply_soft_te() local
6237 ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val, in rockchip_vop2_apply_soft_te()
6247 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, in rockchip_vop2_apply_soft_te()
6270 struct vop2 *vop2 = cstate->private; in rockchip_vop2_regs_dump() local
6271 const struct vop2_data *vop2_data = vop2->data; in rockchip_vop2_regs_dump()
6288 printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4, in rockchip_vop2_regs_dump()
6289 vop2_readl(vop2, base + (4 * j)), in rockchip_vop2_regs_dump()
6290 vop2_readl(vop2, base + (4 * (j + 1))), in rockchip_vop2_regs_dump()
6291 vop2_readl(vop2, base + (4 * (j + 2))), in rockchip_vop2_regs_dump()
6292 vop2_readl(vop2, base + (4 * (j + 3)))); in rockchip_vop2_regs_dump()
6303 struct vop2 *vop2 = cstate->private; in rockchip_vop2_active_regs_dump() local
6304 const struct vop2_data *vop2_data = vop2->data; in rockchip_vop2_active_regs_dump()
6317 enable_state = (vop2_readl(vop2, regs[i].state_base) >> regs[i].state_shift) & in rockchip_vop2_active_regs_dump()
6329 printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4, in rockchip_vop2_active_regs_dump()
6330 vop2_readl(vop2, base + (4 * j)), in rockchip_vop2_active_regs_dump()
6331 vop2_readl(vop2, base + (4 * (j + 1))), in rockchip_vop2_active_regs_dump()
6332 vop2_readl(vop2, base + (4 * (j + 2))), in rockchip_vop2_active_regs_dump()
6333 vop2_readl(vop2, base + (4 * (j + 3)))); in rockchip_vop2_active_regs_dump()
6344 struct vop2 *vop2 = cstate->private; in rk3528_setup_win_dly() local
6349 vop2_mask_write(vop2, RK3528_OVL_SYS_CLUSTER0_CTRL, CLUSTER_DLY_NUM_MASK, in rk3528_setup_win_dly()
6353 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6357 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART1_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6361 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART2_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6365 vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART3_CTRL, ESMART_DLY_NUM_MASK, in rk3528_setup_win_dly()
6374 struct vop2 *vop2 = cstate->private; in rk3528_setup_overlay() local
6381 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3528_setup_overlay()
6383 vop2_writel(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, 0xffffffff); in rk3528_setup_overlay()
6387 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3528_setup_overlay()
6388 if (vop2->vp_plane_mask[i].primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { in rk3528_setup_overlay()
6390 win_data = vop2_find_win_by_phys_id(vop2, vop2->vp_plane_mask[i].primary_plane_id); in rk3528_setup_overlay()
6391 vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, in rk3528_setup_overlay()
6397 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3528_setup_overlay()
6398 if (vop2->vp_plane_mask[i].primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { in rk3528_setup_overlay()
6399 win_data = vop2_find_win_by_phys_id(vop2, vop2->vp_plane_mask[i].primary_plane_id); in rk3528_setup_overlay()
6401 vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL, in rk3528_setup_overlay()
6410 struct vop2 *vop2 = cstate->private; in rk3568_setup_win_dly() local
6414 win_data = vop2_find_win_by_phys_id(vop2, plane_phy_id); in rk3568_setup_win_dly()
6421 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6425 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6429 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM1, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6433 vop2_mask_write(vop2, RK3568_CLUSTER_DLY_NUM1, CLUSTER_DLY_NUM_MASK, in rk3568_setup_win_dly()
6437 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6441 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6446 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6451 vop2_mask_write(vop2, RK3568_SMART_DLY_NUM, SMART_DLY_NUM_MASK, in rk3568_setup_win_dly()
6460 struct vop2 *vop2 = cstate->private; in rk3568_setup_overlay() local
6470 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_setup_overlay()
6471 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in rk3568_setup_overlay()
6473 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in rk3568_setup_overlay()
6474 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); in rk3568_setup_overlay()
6475 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, in rk3568_setup_overlay()
6482 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_setup_overlay()
6483 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; in rk3568_setup_overlay()
6485 if (!vop2->vp_plane_mask[i].attached_layers[j]) in rk3568_setup_overlay()
6487 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; in rk3568_setup_overlay()
6488 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); in rk3568_setup_overlay()
6490 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, in rk3568_setup_overlay()
6498 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3568_setup_overlay()
6500 if (vop2->vp_plane_mask[i].attached_layers_nr) { in rk3568_setup_overlay()
6501 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; in rk3568_setup_overlay()
6507 if (i == vop2->data->nr_vps - 1) in rk3568_setup_overlay()
6508 port_mux = vop2->data->nr_mixers; in rk3568_setup_overlay()
6510 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; in rk3568_setup_overlay()
6511 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, in rk3568_setup_overlay()
6519 struct vop2 *vop2 = cstate->private; in rk3576_setup_win_dly() local
6524 vop2_mask_write(vop2, RK3576_CLUSTER0_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3576_setup_win_dly()
6528 vop2_mask_write(vop2, RK3576_CLUSTER1_DLY_NUM, CLUSTER_DLY_NUM_MASK, in rk3576_setup_win_dly()
6532 vop2_mask_write(vop2, RK3576_ESMART0_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6536 vop2_mask_write(vop2, RK3576_ESMART1_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6540 vop2_mask_write(vop2, RK3576_ESMART2_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6544 vop2_mask_write(vop2, RK3576_ESMART3_DLY_NUM, ESMART_DLY_NUM_MASK, in rk3576_setup_win_dly()
6553 struct vop2 *vop2 = cstate->private; in rk3576_setup_overlay() local
6559 for (i = 0; i < vop2->data->nr_vps; i++) { in rk3576_setup_overlay()
6560 if (vop2->vp_plane_mask[i].primary_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { in rk3576_setup_overlay()
6562 win_data = vop2_find_win_by_phys_id(vop2, vop2->vp_plane_mask[i].primary_plane_id); in rk3576_setup_overlay()
6563 vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + offset, LAYER_SEL_MASK, in rk3576_setup_overlay()