Lines Matching refs:cstate
1635 struct crtc_state *cstate = &state->crtc_state; in vop2_vp_find_attachable_win() local
1636 struct vop2 *vop2 = cstate->private; in vop2_vp_find_attachable_win()
1637 u32 plane_mask = cstate->crtc->vps[vp_id].plane_mask; in vop2_vp_find_attachable_win()
1914 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_gamma_lut_init() local
1928 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); in rockchip_vop2_gamma_lut_init()
1943 if (!cstate->lut_val) { in rockchip_vop2_gamma_lut_init()
1950 cstate->lut_val = (u32 *)calloc(1, lut_size); in rockchip_vop2_gamma_lut_init()
1956 cstate->lut_val[i] = b * lut_len * lut_len + g * lut_len + r; in rockchip_vop2_gamma_lut_init()
1961 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1962 cstate->lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1965 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1966 cstate->lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1967 if (cstate->splice_mode) { in rockchip_vop2_gamma_lut_init()
1968 rk3588_vop2_load_lut(vop2, cstate->splice_crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1969 cstate->lut_val, lut_len); in rockchip_vop2_gamma_lut_init()
1975 free(cstate->lut_val); in rockchip_vop2_gamma_lut_init()
1984 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_cubic_lut_init() local
1986 u32 vp_offset = cstate->crtc_id * 0x100; in rockchip_vop2_cubic_lut_init()
1997 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); in rockchip_vop2_cubic_lut_init()
2022 get_cubic_lut_buffer(cstate->crtc_id)); in rockchip_vop2_cubic_lut_init()
2036 struct crtc_state *cstate = &state->crtc_state; in vop2_bcsh_reg_update() local
2040 BCSH_CTRL_R2Y_SHIFT, cstate->post_r2y_en, false); in vop2_bcsh_reg_update()
2042 BCSH_CTRL_Y2R_SHIFT, cstate->post_y2r_en, false); in vop2_bcsh_reg_update()
2045 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, cstate->post_csc_mode, false); in vop2_bcsh_reg_update()
2047 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, cstate->post_csc_mode, false); in vop2_bcsh_reg_update()
2049 if (!cstate->bcsh_en) { in vop2_bcsh_reg_update()
2078 struct crtc_state *cstate = &state->crtc_state; in vop2_tv_config_update() local
2091 cstate->bcsh_en = true; in vop2_tv_config_update()
2093 if (cstate->bcsh_en) { in vop2_tv_config_update()
2094 if (!cstate->yuv_overlay) in vop2_tv_config_update()
2095 cstate->post_r2y_en = 1; in vop2_tv_config_update()
2097 cstate->post_y2r_en = 1; in vop2_tv_config_update()
2099 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) in vop2_tv_config_update()
2100 cstate->post_r2y_en = 1; in vop2_tv_config_update()
2101 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) in vop2_tv_config_update()
2102 cstate->post_y2r_en = 1; in vop2_tv_config_update()
2105 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_encoding, in vop2_tv_config_update()
2109 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) in vop2_tv_config_update()
2137 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); in vop2_tv_config_update()
2138 if (cstate->splice_mode) in vop2_tv_config_update()
2139 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); in vop2_tv_config_update()
2146 struct crtc_state *cstate = &state->crtc_state; in vop2_setup_dly_for_vp() local
2151 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; in vop2_setup_dly_for_vp()
2159 if (cstate->splice_mode) in vop2_setup_dly_for_vp()
2199 struct crtc_state *cstate = &state->crtc_state; in vop2_post_config() local
2202 struct vop2_vp_plane_mask *plane_mask = &vop2->vp_plane_mask[cstate->crtc_id]; in vop2_post_config()
2203 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_config()
2223 cstate->overscan_by_win_scale = true; in vop2_post_config()
2262 vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); in vop2_post_config()
2264 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); in vop2_post_config()
2265 vop2_ops->setup_win_dly(state, cstate->crtc_id, plane_mask->primary_plane_id); in vop2_post_config()
2266 if (cstate->splice_mode) { in vop2_post_config()
2267 plane_mask = &vop2->vp_plane_mask[cstate->splice_crtc_id]; in vop2_post_config()
2268 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); in vop2_post_config()
2269 vop2_ops->setup_win_dly(state, cstate->splice_crtc_id, plane_mask->primary_plane_id); in vop2_post_config()
2277 struct crtc_state *cstate = &state->crtc_state; in vop3_post_acm_config() local
2280 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_acm_config()
2374 struct crtc_state *cstate = &state->crtc_state; in vop3_post_csc_config() local
2382 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_csc_config()
2392 if (!cstate->yuv_overlay) in vop3_post_csc_config()
2399 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) in vop3_post_csc_config()
2403 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) in vop3_post_csc_config()
2410 if (cstate->yuv_overlay || post_r2y_en) in vop3_post_csc_config()
2416 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_encoding, in vop3_post_csc_config()
2421 rockchip_calc_post_csc(csc, &csc_coef, cstate->post_csc_mode, is_input_yuv, in vop3_post_csc_config()
2454 POST_R2Y_MODE_MASK, POST_R2Y_MODE_SHIFT, cstate->post_csc_mode, false); in vop3_post_csc_config()
2685 struct crtc_state *cstate = &state->crtc_state; in vop2_plane_mask_to_possible_vp_mask() local
2686 struct vop2 *vop2 = cstate->private; in vop2_plane_mask_to_possible_vp_mask()
2700 plane_mask = cstate->crtc->vps[i].plane_mask; in vop2_plane_mask_to_possible_vp_mask()
2718 struct crtc_state *cstate = &state->crtc_state; in vop2_plane_mask_check() local
2719 struct vop2 *vop2 = cstate->private; in vop2_plane_mask_check()
2733 plane_mask = cstate->crtc->vps[i].plane_mask; in vop2_plane_mask_check()
2734 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; in vop2_plane_mask_check()
2735 cursor_plane_id = cstate->crtc->vps[i].cursor_plane_id; in vop2_plane_mask_check()
2791 if (assigned_plane_mask & cstate->crtc->vps[i].plane_mask) { in vop2_plane_mask_check()
2795 assigned_plane_mask |= cstate->crtc->vps[i].plane_mask; in vop2_plane_mask_check()
2815 struct crtc_state *cstate = &state->crtc_state; in rockchip_cursor_plane_assign() local
2816 struct vop2 *vop2 = cstate->private; in rockchip_cursor_plane_assign()
2820 if (cstate->crtc->vps[vp_id].cursor_plane_id != ROCKCHIP_VOP2_PHY_ID_INVALID) { in rockchip_cursor_plane_assign()
2821 win_data = vop2_find_win_by_phys_id(vop2, cstate->crtc->vps[vp_id].cursor_plane_id); in rockchip_cursor_plane_assign()
2825 cstate->crtc->vps[vp_id].cursor_plane_id; in rockchip_cursor_plane_assign()
2864 struct crtc_state *cstate = &state->crtc_state; in rk3528_assign_plane_mask() local
2865 struct vop2 *vop2 = cstate->private; in rk3528_assign_plane_mask()
2873 if (!cstate->crtc->vps[i].enable) in rk3528_assign_plane_mask()
2912 struct crtc_state *cstate = &state->crtc_state; in rk3568_assign_plane_mask() local
2913 struct vop2 *vop2 = cstate->private; in rk3568_assign_plane_mask()
2924 if (cstate->crtc->vps[i].enable) in rk3568_assign_plane_mask()
2943 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { in rk3568_assign_plane_mask()
2970 if (i == main_vp_index || !cstate->crtc->vps[i].enable) in rk3568_assign_plane_mask()
3003 if (cstate->crtc->vps[i].enable) in rk3568_assign_plane_mask()
3010 struct crtc_state *cstate = &state->crtc_state; in vop2_global_initial() local
3043 if (cstate->crtc->assign_plane) { in vop2_global_initial()
3047 plane_mask = cstate->crtc->vps[i].plane_mask; in vop2_global_initial()
3050 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; in vop2_global_initial()
3112 tmp = dev_read_u8_array_ptr(cstate->dev, "esmart_lb_mode", 1); in vop2_global_initial()
3158 vop2->merge_irq = ofnode_read_bool(cstate->node, "rockchip,vop-merge-irq"); in vop2_global_initial()
3185 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_sharp_init() local
3187 const struct vop2_vp_data *vp_data = &vop2_data->vp_data[cstate->crtc_id]; in rockchip_vop2_sharp_init()
3188 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; in rockchip_vop2_sharp_init()
3195 ret = ofnode_read_resource_byname(cstate->node, "sharp_regs", &sharp_regs); in rockchip_vop2_sharp_init()
3211 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_acm_init() local
3213 const struct vop2_vp_data *vp_data = &vop2_data->vp_data[cstate->crtc_id]; in rockchip_vop2_acm_init()
3216 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_acm_init()
3222 ret = ofnode_read_resource_byname(cstate->node, "acm_regs", &acm_regs); in rockchip_vop2_acm_init()
3243 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_of_get_gamma_lut() local
3258 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); in rockchip_vop2_of_get_gamma_lut()
3269 cstate->lut_val = (u32 *)calloc(1, lut_size); in rockchip_vop2_of_get_gamma_lut()
3270 if (!cstate->lut_val) in rockchip_vop2_of_get_gamma_lut()
3277 free(cstate->lut_val); in rockchip_vop2_of_get_gamma_lut()
3283 printf("Failed to load gamma-lut for vp%d\n", cstate->crtc_id); in rockchip_vop2_of_get_gamma_lut()
3284 free(cstate->lut_val); in rockchip_vop2_of_get_gamma_lut()
3300 cstate->lut_val[i] = r * lut_len * lut_len + g * lut_len + b; in rockchip_vop2_of_get_gamma_lut()
3304 of_read_u32_array(dsp_lut_node, "gamma-lut", cstate->lut_val, lut_len); in rockchip_vop2_of_get_gamma_lut()
3312 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_of_get_dsp_lut() local
3317 phandle = ofnode_read_u32_default(np_to_ofnode(cstate->port_node), "dsp-lut", -1); in rockchip_vop2_of_get_dsp_lut()
3327 printf("failed to load vp%d gamma-lut from dts\n", cstate->crtc_id); in rockchip_vop2_of_get_dsp_lut()
3348 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_preinit() local
3349 const struct vop2_data *vop2_data = cstate->crtc->data; in rockchip_vop2_preinit()
3368 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); in rockchip_vop2_preinit()
3369 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,grf"); in rockchip_vop2_preinit()
3377 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vop-grf"); in rockchip_vop2_preinit()
3382 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vo1-grf"); in rockchip_vop2_preinit()
3387 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,pmu"); in rockchip_vop2_preinit()
3393 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,ioc-grf"); in rockchip_vop2_preinit()
3398 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,pmu"); in rockchip_vop2_preinit()
3405 ret = power_domain_get(cstate->dev, &pwrdom); in rockchip_vop2_preinit()
3415 ret = clk_get_bulk(cstate->dev, &clks); in rockchip_vop2_preinit()
3431 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); in rockchip_vop2_preinit()
3432 if (dev_read_stringlist_search(cstate->dev, "reset-names", dclk_name) > 0) { in rockchip_vop2_preinit()
3433 ret = reset_get_by_name(cstate->dev, dclk_name, &cstate->dclk_rst); in rockchip_vop2_preinit()
3436 cstate->dclk_rst.dev = NULL; in rockchip_vop2_preinit()
3440 cstate->private = rockchip_vop2; in rockchip_vop2_preinit()
3441 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; in rockchip_vop2_preinit()
3442 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; in rockchip_vop2_preinit()
3476 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_cru_cfg() local
3479 struct vop2 *vop2 = cstate->private; in vop2_calc_cru_cfg()
3510 if (cstate->dsc_enable) { in vop2_calc_cru_cfg()
3511 if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; in vop2_calc_cru_cfg()
3512 if_dclk_rate = cstate->dsc_cds_clk_rate; in vop2_calc_cru_cfg()
3520 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3524 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, if_pixclk_rate); in vop2_calc_cru_cfg()
3531 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
3548 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3551 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, dclk_core_rate); in vop2_calc_cru_cfg()
3559 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
3561 if_pixclk_rate = cstate->dsc_cds_clk_rate >> 1; in vop2_calc_cru_cfg()
3568 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3571 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, dclk_rate); in vop2_calc_cru_cfg()
3575 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
3576 dclk_rate /= cstate->dsc_slice_num; in vop2_calc_cru_cfg()
3581 if (cstate->dsc_enable) in vop2_calc_cru_cfg()
3598 (output_type == DRM_MODE_CONNECTOR_HDMIA && cstate->dsc_enable)) in vop2_calc_cru_cfg()
3610 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_dsc_clk() local
3617 cstate->dsc_txp_clk_rate = v_pixclk; in vop2_calc_dsc_clk()
3618 do_div(cstate->dsc_txp_clk_rate, (cstate->dsc_pixel_num * k)); in vop2_calc_dsc_clk()
3620 cstate->dsc_pxl_clk_rate = v_pixclk; in vop2_calc_dsc_clk()
3621 do_div(cstate->dsc_pxl_clk_rate, (cstate->dsc_slice_num * k)); in vop2_calc_dsc_clk()
3630 cstate->dsc_cds_clk_rate = v_pixclk / (cstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8); in vop2_calc_dsc_clk()
3637 struct crtc_state *cstate = &state->crtc_state; in rk3588_vop2_if_cfg() local
3640 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; in rk3588_vop2_if_cfg()
3641 struct vop2 *vop2 = cstate->private; in rk3588_vop2_if_cfg()
3642 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3588_vop2_if_cfg()
3660 if (cstate->dsc_enable) { in rk3588_vop2_if_cfg()
3671 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; in rk3588_vop2_if_cfg()
3672 cstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k; in rk3588_vop2_if_cfg()
3673 cstate->dsc_pixel_num = cstate->dsc_slice_num > 4 ? 4 : cstate->dsc_slice_num; in rk3588_vop2_if_cfg()
3677 cstate->dsc_id, dsc_sink_cap->slice_width, in rk3588_vop2_if_cfg()
3678 dsc_sink_cap->slice_height, cstate->dsc_slice_num); in rk3588_vop2_if_cfg()
3681 …dclk_rate = vop2_calc_cru_cfg(state, &cstate->dclk_core_div, &cstate->dclk_out_div, &if_pixclk_div… in rk3588_vop2_if_cfg()
3711 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
3728 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3588_vop2_if_cfg()
3735 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
3737 else if (cstate->crtc_id == 3) in rk3588_vop2_if_cfg()
3754 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3588_vop2_if_cfg()
3793 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3808 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3823 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3830 if (cstate->dsc_enable) in rk3588_vop2_if_cfg()
3845 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3852 if (cstate->dsc_enable) in rk3588_vop2_if_cfg()
3865 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3872 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3878 DCLK_CORE_DIV_SHIFT, cstate->dclk_core_div, false); in rk3588_vop2_if_cfg()
3880 DCLK_OUT_DIV_SHIFT, cstate->dclk_out_div, false); in rk3588_vop2_if_cfg()
3887 struct crtc_state *cstate = &state->crtc_state; in rk3576_vop2_if_cfg() local
3890 struct vop2 *vop2 = cstate->private; in rk3576_vop2_if_cfg()
3891 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3576_vop2_if_cfg()
3892 u8 port_pix_rate = vop2->data->vp_data[cstate->crtc_id].pixel_rate; in rk3576_vop2_if_cfg()
3915 if (vop2->data->vp_data[cstate->crtc_id].feature & VOP_FEATURE_POST_SHARP) in rk3576_vop2_if_cfg()
3933 mode->crtc_clock > VOP2_MAX_DCLK_RATE || (cstate->crtc_id == 0 && split_mode)) in rk3576_vop2_if_cfg()
3934 cstate->crtc->vps[cstate->crtc_id].dclk_div = 2; /* div2 */ in rk3576_vop2_if_cfg()
3936 cstate->crtc->vps[cstate->crtc_id].dclk_div = 1; /* no div */ in rk3576_vop2_if_cfg()
3937 dclk_in_rate = mode->crtc_clock / cstate->crtc->vps[cstate->crtc_id].dclk_div; in rk3576_vop2_if_cfg()
3983 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4004 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4026 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4048 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4064 EDPI_TE_EN, !cstate->soft_te, false); in rk3576_vop2_if_cfg()
4112 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4131 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4148 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4165 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4182 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4192 struct crtc_state *cstate = &state->crtc_state; in rk3568_vop2_setup_dual_channel_if() local
4194 struct vop2 *vop2 = cstate->private; in rk3568_vop2_setup_dual_channel_if()
4195 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3568_vop2_setup_dual_channel_if()
4227 struct crtc_state *cstate = &state->crtc_state; in rk3568_vop2_if_cfg() local
4230 struct vop2 *vop2 = cstate->private; in rk3568_vop2_if_cfg()
4242 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4255 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4264 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4273 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4284 LVDS1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4296 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4307 MIPI1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4324 EDP0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4335 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4348 struct crtc_state *cstate = &state->crtc_state; in rk3562_vop2_if_cfg() local
4351 struct vop2 *vop2 = cstate->private; in rk3562_vop2_if_cfg()
4353 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3562_vop2_if_cfg()
4364 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
4375 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
4386 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
4394 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3562_vop2_if_cfg()
4405 struct crtc_state *cstate = &state->crtc_state; in rk3528_vop2_if_cfg() local
4408 struct vop2 *vop2 = cstate->private; in rk3528_vop2_if_cfg()
4418 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
4425 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
4438 struct crtc_state *cstate = &state->crtc_state; in vop2_post_color_swap() local
4440 struct vop2 *vop2 = cstate->private; in vop2_post_color_swap()
4441 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_color_swap()
4489 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_dsc_cru_cfg() local
4491 *dsc_txp_clk_div = dclk_rate / cstate->dsc_txp_clk_rate; in vop2_calc_dsc_cru_cfg()
4492 *dsc_pxl_clk_div = dclk_rate / cstate->dsc_pxl_clk_rate; in vop2_calc_dsc_cru_cfg()
4493 *dsc_cds_clk_div = dclk_rate / cstate->dsc_cds_clk_rate; in vop2_calc_dsc_cru_cfg()
4502 struct crtc_state *cstate = &state->crtc_state; in vop2_load_pps() local
4503 struct drm_dsc_picture_parameter_set *pps = &cstate->pps; in vop2_load_pps()
4536 struct crtc_state *cstate = &state->crtc_state; in vop2_dsc_enable() local
4537 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; in vop2_dsc_enable()
4563 if (cstate->dsc_slice_num > dsc_data->max_slice_num) in vop2_dsc_enable()
4565 dsc_data->id, dsc_data->max_slice_num, cstate->dsc_slice_num); in vop2_dsc_enable()
4575 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); in vop2_dsc_enable()
4598 DSC_PIXEL_NUM_SHIFT, cstate->dsc_pixel_num >> 1, false); in vop2_dsc_enable()
4613 u64 dsc_cds_rate = cstate->dsc_cds_clk_rate; in vop2_dsc_enable()
4649 int delay_line_num = dsc_buf_size / cstate->dsc_slice_num / in vop2_dsc_enable()
4650 be16_to_cpu(cstate->pps.chunk_size); in vop2_dsc_enable()
4674 dsc_htotal = htotal * (1 << cstate->dclk_core_div) / in vop2_dsc_enable()
4696 val |= DSC_CTRL0_DEF_CON | (ilog2(cstate->dsc_slice_num) << DSC_NSLC_SHIFT) | in vop2_dsc_enable()
4707 cstate->dsc_txp_clk_rate, dsc_txp_clk_div, in vop2_dsc_enable()
4708 cstate->dsc_pxl_clk_rate, dsc_pxl_clk_div, in vop2_dsc_enable()
4709 cstate->dsc_cds_clk_rate, dsc_cds_clk_div); in vop2_dsc_enable()
4714 struct crtc_state *cstate = &state->crtc_state; in is_extend_pll() local
4715 struct vop2 *vop2 = cstate->private; in is_extend_pll()
4724 sprintf(vp_name, "port@%d", cstate->crtc_id); in is_extend_pll()
4754 struct crtc_state *cstate = &state->crtc_state; in vop3_mcu_mode_setup() local
4755 struct vop2 *vop2 = cstate->private; in vop3_mcu_mode_setup()
4756 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_mode_setup()
4763 MCU_PIX_TOTAL_SHIFT, cstate->mcu_timing.mcu_pix_total, false); in vop3_mcu_mode_setup()
4765 MCU_CS_PST_SHIFT, cstate->mcu_timing.mcu_cs_pst, false); in vop3_mcu_mode_setup()
4767 MCU_CS_PEND_SHIFT, cstate->mcu_timing.mcu_cs_pend, false); in vop3_mcu_mode_setup()
4769 MCU_RW_PST_SHIFT, cstate->mcu_timing.mcu_rw_pst, false); in vop3_mcu_mode_setup()
4771 MCU_RW_PEND_SHIFT, cstate->mcu_timing.mcu_rw_pend, false); in vop3_mcu_mode_setup()
4776 struct crtc_state *cstate = &state->crtc_state; in vop3_mcu_bypass_mode_setup() local
4777 struct vop2 *vop2 = cstate->private; in vop3_mcu_bypass_mode_setup()
4778 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_bypass_mode_setup()
4798 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_send_mcu_cmd() local
4801 struct vop2 *vop2 = cstate->private; in rockchip_vop2_send_mcu_cmd()
4802 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_send_mcu_cmd()
4810 vop2_clk_set_rate(&cstate->dclk, 150000000); in rockchip_vop2_send_mcu_cmd()
4844 vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000); in rockchip_vop2_send_mcu_cmd()
4930 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_init() local
4931 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; in rockchip_vop2_init()
4934 struct vop2 *vop2 = cstate->private; in rockchip_vop2_init()
4946 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_init()
4947 u32 line_flag_offset = (cstate->crtc_id * 4); in rockchip_vop2_init()
4949 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_init()
4968 cstate->crtc_id); in rockchip_vop2_init()
4971 cstate->splice_mode = true; in rockchip_vop2_init()
4972 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; in rockchip_vop2_init()
4973 if (!cstate->splice_crtc_id) { in rockchip_vop2_init()
4975 __func__, cstate->crtc_id); in rockchip_vop2_init()
4984 RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
4986 RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
4988 if (vop2->data->vp_data[cstate->crtc_id].urgency) { in rockchip_vop2_init()
4989 u8 urgen_thl = vop2->data->vp_data[cstate->crtc_id].urgency->urgen_thl; in rockchip_vop2_init()
4990 u8 urgen_thh = vop2->data->vp_data[cstate->crtc_id].urgency->urgen_thh; in rockchip_vop2_init()
4993 AXI0_PORT_URGENCY_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
4995 AXI1_PORT_URGENCY_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
5017 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) || in rockchip_vop2_init()
5044 vop2_dither_setup(vop2, conn_state->bus_format, cstate->crtc_id); in rockchip_vop2_init()
5045 if (cstate->splice_mode) in rockchip_vop2_init()
5046 vop2_dither_setup(vop2, conn_state->bus_format, cstate->splice_crtc_id); in rockchip_vop2_init()
5049 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
5052 cstate->yuv_overlay = yuv_overlay; in rockchip_vop2_init()
5110 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); in rockchip_vop2_init()
5117 if (cstate->splice_mode) { in rockchip_vop2_init()
5119 OVL_MODE_SEL_SHIFT + cstate->splice_crtc_id, in rockchip_vop2_init()
5121 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); in rockchip_vop2_init()
5133 if (cstate->feature & (VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC)) in rockchip_vop2_init()
5136 if (cstate->dsc_enable) { in rockchip_vop2_init()
5141 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL); in rockchip_vop2_init()
5146 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); in rockchip_vop2_init()
5147 ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk); in rockchip_vop2_init()
5171 ret = dev_read_phandle_with_args(cstate->dev, "assigned-clock-parents", in rockchip_vop2_init()
5185 vp_dclk_div = cstate->crtc->vps[cstate->crtc_id].dclk_div; in rockchip_vop2_init()
5189 vop2_clk_set_parent(&cstate->dclk, &hdmi0_phy_pll); in rockchip_vop2_init()
5191 vop2_clk_set_parent(&cstate->dclk, &hdmi1_phy_pll); in rockchip_vop2_init()
5209 ret = vop2_clk_set_rate(&cstate->dclk, in rockchip_vop2_init()
5227 ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate / vp_dclk_div * 1000); in rockchip_vop2_init()
5232 __func__, cstate->crtc_id, dclk_rate, ret); in rockchip_vop2_init()
5235 if (cstate->mcu_timing.mcu_pix_total) { in rockchip_vop2_init()
5241 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); in rockchip_vop2_init()
5249 if (cstate->mcu_timing.mcu_pix_total) { in rockchip_vop2_init()
5495 struct crtc_state *cstate = &state->crtc_state; in vop2_set_cluster_win() local
5498 struct vop2 *vop2 = cstate->private; in vop2_set_cluster_win()
5501 int src_w = cstate->src_rect.w; in vop2_set_cluster_win()
5502 int src_h = cstate->src_rect.h; in vop2_set_cluster_win()
5503 int crtc_x = cstate->crtc_rect.x; in vop2_set_cluster_win()
5504 int crtc_y = cstate->crtc_rect.y; in vop2_set_cluster_win()
5505 int crtc_w = cstate->crtc_rect.w; in vop2_set_cluster_win()
5506 int crtc_h = cstate->crtc_rect.h; in vop2_set_cluster_win()
5507 int xvir = cstate->xvir; in vop2_set_cluster_win()
5518 src_w = cstate->right_src_rect.w; in vop2_set_cluster_win()
5519 src_h = cstate->right_src_rect.h; in vop2_set_cluster_win()
5520 crtc_x = cstate->right_crtc_rect.x; in vop2_set_cluster_win()
5521 crtc_y = cstate->right_crtc_rect.y; in vop2_set_cluster_win()
5522 crtc_w = cstate->right_crtc_rect.w; in vop2_set_cluster_win()
5523 crtc_h = cstate->right_crtc_rect.h; in vop2_set_cluster_win()
5524 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; in vop2_set_cluster_win()
5554 cstate->crtc_id, false); in vop2_set_cluster_win()
5555 vop2_ops->setup_win_dly(state, cstate->crtc_id, win->phys_id); in vop2_set_cluster_win()
5566 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, in vop2_set_cluster_win()
5569 0x1, CLUSTER_RB_SWAP_SHIFT, cstate->rb_swap, false); in vop2_set_cluster_win()
5572 cstate->dma_addr + splice_yrgb_offset); in vop2_set_cluster_win()
5586 dither_up = vop2_win_dither_up(cstate->format); in vop2_set_cluster_win()
5598 struct crtc_state *cstate = &state->crtc_state; in vop2_set_smart_win() local
5601 struct vop2 *vop2 = cstate->private; in vop2_set_smart_win()
5604 int src_w = cstate->src_rect.w; in vop2_set_smart_win()
5605 int src_h = cstate->src_rect.h; in vop2_set_smart_win()
5606 int crtc_x = cstate->crtc_rect.x; in vop2_set_smart_win()
5607 int crtc_y = cstate->crtc_rect.y; in vop2_set_smart_win()
5608 int crtc_w = cstate->crtc_rect.w; in vop2_set_smart_win()
5609 int crtc_h = cstate->crtc_rect.h; in vop2_set_smart_win()
5610 int xvir = cstate->xvir; in vop2_set_smart_win()
5637 src_w = cstate->right_src_rect.w; in vop2_set_smart_win()
5638 src_h = cstate->right_src_rect.h; in vop2_set_smart_win()
5639 crtc_x = cstate->right_crtc_rect.x; in vop2_set_smart_win()
5640 crtc_y = cstate->right_crtc_rect.y; in vop2_set_smart_win()
5641 crtc_w = cstate->right_crtc_rect.w; in vop2_set_smart_win()
5642 crtc_h = cstate->right_crtc_rect.h; in vop2_set_smart_win()
5643 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; in vop2_set_smart_win()
5652 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); in vop2_set_smart_win()
5677 cstate->crtc_id, false); in vop2_set_smart_win()
5678 vop2_ops->setup_win_dly(state, cstate->crtc_id, win->phys_id); in vop2_set_smart_win()
5681 if (vop2->version == VOP_VERSION_RK3576 && cstate->crtc_id == 0 && in vop2_set_smart_win()
5695 cstate->dma_addr += (src_h - 1) * xvir * 4; in vop2_set_smart_win()
5700 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, in vop2_set_smart_win()
5704 0x1, REGION0_RB_SWAP_SHIFT, cstate->rb_swap, false); in vop2_set_smart_win()
5711 cstate->dma_addr + splice_yrgb_offset); in vop2_set_smart_win()
5727 dither_up = vop2_win_dither_up(cstate->format); in vop2_set_smart_win()
5739 struct crtc_state *cstate = &state->crtc_state; in vop2_calc_display_rect_for_splice() local
5742 struct display_rect *src_rect = &cstate->src_rect; in vop2_calc_display_rect_for_splice()
5743 struct display_rect *dst_rect = &cstate->crtc_rect; in vop2_calc_display_rect_for_splice()
5776 memcpy(&cstate->src_rect, &left_src, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
5777 memcpy(&cstate->crtc_rect, &left_dst, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
5778 memcpy(&cstate->right_src_rect, &right_src, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
5779 memcpy(&cstate->right_crtc_rect, &right_dst, sizeof(struct display_rect)); in vop2_calc_display_rect_for_splice()
5784 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_set_plane() local
5785 struct vop2 *vop2 = cstate->private; in rockchip_vop2_set_plane()
5788 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_set_plane()
5791 if (cstate->crtc_rect.w > cstate->max_output.width) { in rockchip_vop2_set_plane()
5793 cstate->crtc_rect.w, cstate->max_output.width); in rockchip_vop2_set_plane()
5809 printf("open vp%d plane pd fail\n", cstate->crtc_id); in rockchip_vop2_set_plane()
5812 if (cstate->splice_mode) { in rockchip_vop2_set_plane()
5818 printf("splice mode: open vp%d plane pd fail\n", cstate->splice_crtc_id); in rockchip_vop2_set_plane()
5840 cstate->crtc_id, vop2_plane_phys_id_to_string(primary_plane_id), in rockchip_vop2_set_plane()
5841 cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, in rockchip_vop2_set_plane()
5842 cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, in rockchip_vop2_set_plane()
5843 cstate->dma_addr); in rockchip_vop2_set_plane()
5856 struct crtc_state *cstate = &state->crtc_state; in vop2_dsc_cfg_done() local
5857 struct vop2 *vop2 = cstate->private; in vop2_dsc_cfg_done()
5858 u8 dsc_id = cstate->dsc_id; in vop2_dsc_cfg_done()
5874 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_enable() local
5875 struct vop2 *vop2 = cstate->private; in rockchip_vop2_enable()
5876 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_enable()
5877 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_enable()
5882 if (cstate->splice_mode) in rockchip_vop2_enable()
5883 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); in rockchip_vop2_enable()
5887 if (cstate->dsc_enable) in rockchip_vop2_enable()
5890 if (cstate->mcu_timing.mcu_pix_total) in rockchip_vop2_enable()
5900 struct crtc_state *cstate = &state->crtc_state; in rk3588_vop2_post_enable() local
5901 struct vop2 *vop2 = cstate->private; in rk3588_vop2_post_enable()
5903 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rk3588_vop2_post_enable()
5917 val & BIT(cstate->crtc_id), 50 * 1000); in rk3588_vop2_post_enable()
5921 if (cstate->dclk_rst.dev) { in rk3588_vop2_post_enable()
5922 reset_assert(&cstate->dclk_rst); in rk3588_vop2_post_enable()
5924 reset_deassert(&cstate->dclk_rst); in rk3588_vop2_post_enable()
5934 struct crtc_state *cstate = &state->crtc_state; in rk3576_vop2_post_enable() local
5935 struct vop2 *vop2 = cstate->private; in rk3576_vop2_post_enable()
5937 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rk3576_vop2_post_enable()
5955 val & BIT(cstate->crtc_id), 50 * 1000); in rk3576_vop2_post_enable()
5959 if (cstate->dclk_rst.dev) { in rk3576_vop2_post_enable()
5960 reset_assert(&cstate->dclk_rst); in rk3576_vop2_post_enable()
5962 reset_deassert(&cstate->dclk_rst); in rk3576_vop2_post_enable()
5971 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_post_enable() local
5972 struct vop2 *vop2 = cstate->private; in rockchip_vop2_post_enable()
5984 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_disable() local
5985 struct vop2 *vop2 = cstate->private; in rockchip_vop2_disable()
5986 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_disable()
5987 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_disable()
5992 if (cstate->splice_mode) in rockchip_vop2_disable()
5993 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); in rockchip_vop2_disable()
6002 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_fixup_dts() local
6003 struct vop2 *vop2 = cstate->private; in rockchip_vop2_fixup_dts()
6005 struct device_node *port_parent_node = cstate->ports_node; in rockchip_vop2_fixup_dts()
6025 if (cstate->crtc->assign_plane) in rockchip_vop2_fixup_dts()
6050 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_check() local
6051 struct rockchip_crtc *crtc = cstate->crtc; in rockchip_vop2_check()
6053 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { in rockchip_vop2_check()
6054 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); in rockchip_vop2_check()
6058 if (cstate->splice_mode) { in rockchip_vop2_check()
6060 crtc->splice_crtc_id = cstate->splice_crtc_id; in rockchip_vop2_check()
6069 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_mode_valid() local
6078 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); in rockchip_vop2_mode_valid()
6090 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_mode_fixup() local
6091 struct vop2 *vop2 = cstate->private; in rockchip_vop2_mode_fixup()
6142 if (cstate->dsc_sink_cap.target_bits_per_pixel_x16 < 0x90 && in rockchip_vop2_mode_fixup()
6143 cstate->dsc_enable) { in rockchip_vop2_mode_fixup()
6190 if (cstate->mcu_timing.mcu_pix_total) in rockchip_vop2_mode_fixup()
6191 mode->crtc_clock *= cstate->mcu_timing.mcu_pix_total + 1; in rockchip_vop2_mode_fixup()
6200 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_plane_check() local
6201 struct vop2 *vop2 = cstate->private; in rockchip_vop2_plane_check()
6202 struct display_rect *src = &cstate->src_rect; in rockchip_vop2_plane_check()
6203 struct display_rect *dst = &cstate->crtc_rect; in rockchip_vop2_plane_check()
6207 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_plane_check()
6221 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); in rockchip_vop2_plane_check()
6231 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_apply_soft_te() local
6232 struct vop2 *vop2 = cstate->private; in rockchip_vop2_apply_soft_te()
6233 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_apply_soft_te()
6251 cstate->crtc_id); in rockchip_vop2_apply_soft_te()
6255 printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
6260 printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
6269 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_regs_dump() local
6270 struct vop2 *vop2 = cstate->private; in rockchip_vop2_regs_dump()
6277 if (!cstate->crtc->active) in rockchip_vop2_regs_dump()
6302 struct crtc_state *cstate = &state->crtc_state; in rockchip_vop2_active_regs_dump() local
6303 struct vop2 *vop2 = cstate->private; in rockchip_vop2_active_regs_dump()
6311 if (!cstate->crtc->active) in rockchip_vop2_active_regs_dump()
6343 struct crtc_state *cstate = &state->crtc_state; in rk3528_setup_win_dly() local
6344 struct vop2 *vop2 = cstate->private; in rk3528_setup_win_dly()
6373 struct crtc_state *cstate = &state->crtc_state; in rk3528_setup_overlay() local
6374 struct vop2 *vop2 = cstate->private; in rk3528_setup_overlay()
6409 struct crtc_state *cstate = &state->crtc_state; in rk3568_setup_win_dly() local
6410 struct vop2 *vop2 = cstate->private; in rk3568_setup_win_dly()
6459 struct crtc_state *cstate = &state->crtc_state; in rk3568_setup_overlay() local
6460 struct vop2 *vop2 = cstate->private; in rk3568_setup_overlay()
6510 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; in rk3568_setup_overlay()
6518 struct crtc_state *cstate = &state->crtc_state; in rk3576_setup_win_dly() local
6519 struct vop2 *vop2 = cstate->private; in rk3576_setup_win_dly()
6552 struct crtc_state *cstate = &state->crtc_state; in rk3576_setup_overlay() local
6553 struct vop2 *vop2 = cstate->private; in rk3576_setup_overlay()