Lines Matching refs:crtc_id
1423 void (*setup_win_dly)(struct display_state *state, int crtc_id, u8 plane_phy_id);
1869 static void rk3568_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3568_vop2_load_lut() argument
1872 u32 vp_offset = crtc_id * 0x100; in rk3568_vop2_load_lut()
1877 crtc_id, false); in rk3568_vop2_load_lut()
1886 static void rk3588_vop2_load_lut(struct vop2 *vop2, int crtc_id, in rk3588_vop2_load_lut() argument
1889 u32 vp_offset = crtc_id * 0x100; in rk3588_vop2_load_lut()
1895 crtc_id, true); in rk3588_vop2_load_lut()
1899 crtc_id, false); in rk3588_vop2_load_lut()
1961 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1965 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, in rockchip_vop2_gamma_lut_init()
1986 u32 vp_offset = cstate->crtc_id * 0x100; in rockchip_vop2_cubic_lut_init()
1997 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); in rockchip_vop2_cubic_lut_init()
2022 get_cubic_lut_buffer(cstate->crtc_id)); in rockchip_vop2_cubic_lut_init()
2034 struct bcsh_state *bcsh_state, int crtc_id) in vop2_bcsh_reg_update() argument
2037 u32 vp_offset = crtc_id * 0x100; in vop2_bcsh_reg_update()
2137 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); in vop2_tv_config_update()
2142 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop2_setup_dly_for_vp() argument
2151 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; in vop2_setup_dly_for_vp()
2152 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; in vop2_setup_dly_for_vp()
2167 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, in vop2_setup_dly_for_vp()
2169 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop2_setup_dly_for_vp()
2172 static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, int crtc_id) in vop3_setup_pipe_dly() argument
2180 bg_dly = vop2->data->vp_data[crtc_id].win_dly + in vop3_setup_pipe_dly()
2181 vop2->data->vp_data[crtc_id].layer_mix_dly + in vop3_setup_pipe_dly()
2182 vop2->data->vp_data[crtc_id].hdr_mix_dly; in vop3_setup_pipe_dly()
2190 vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100, in vop3_setup_pipe_dly()
2192 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); in vop3_setup_pipe_dly()
2202 struct vop2_vp_plane_mask *plane_mask = &vop2->vp_plane_mask[cstate->crtc_id]; in vop2_post_config()
2203 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_config()
2262 vop3_setup_pipe_dly(state, vop2, cstate->crtc_id); in vop2_post_config()
2264 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); in vop2_post_config()
2265 vop2_ops->setup_win_dly(state, cstate->crtc_id, plane_mask->primary_plane_id); in vop2_post_config()
2280 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_acm_config()
2382 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_post_csc_config()
3187 const struct vop2_vp_data *vp_data = &vop2_data->vp_data[cstate->crtc_id]; in rockchip_vop2_sharp_init()
3188 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; in rockchip_vop2_sharp_init()
3213 const struct vop2_vp_data *vp_data = &vop2_data->vp_data[cstate->crtc_id]; in rockchip_vop2_acm_init()
3216 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_acm_init()
3283 printf("Failed to load gamma-lut for vp%d\n", cstate->crtc_id); in rockchip_vop2_of_get_gamma_lut()
3327 printf("failed to load vp%d gamma-lut from dts\n", cstate->crtc_id); in rockchip_vop2_of_get_dsp_lut()
3431 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); in rockchip_vop2_preinit()
3441 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; in rockchip_vop2_preinit()
3442 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; in rockchip_vop2_preinit()
3520 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3524 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, if_pixclk_rate); in vop2_calc_cru_cfg()
3548 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3551 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, dclk_core_rate); in vop2_calc_cru_cfg()
3568 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L); in vop2_calc_cru_cfg()
3571 vop2->data->vp_data[cstate->crtc_id].max_dclk * 1000L, dclk_rate); in vop2_calc_cru_cfg()
3642 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3588_vop2_if_cfg()
3711 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
3735 if (cstate->crtc_id == 2) in rk3588_vop2_if_cfg()
3737 else if (cstate->crtc_id == 3) in rk3588_vop2_if_cfg()
3793 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3808 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3823 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3845 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3865 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3872 cstate->crtc_id, false); in rk3588_vop2_if_cfg()
3891 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3576_vop2_if_cfg()
3892 u8 port_pix_rate = vop2->data->vp_data[cstate->crtc_id].pixel_rate; in rk3576_vop2_if_cfg()
3915 if (vop2->data->vp_data[cstate->crtc_id].feature & VOP_FEATURE_POST_SHARP) in rk3576_vop2_if_cfg()
3933 mode->crtc_clock > VOP2_MAX_DCLK_RATE || (cstate->crtc_id == 0 && split_mode)) in rk3576_vop2_if_cfg()
3934 cstate->crtc->vps[cstate->crtc_id].dclk_div = 2; /* div2 */ in rk3576_vop2_if_cfg()
3936 cstate->crtc->vps[cstate->crtc_id].dclk_div = 1; /* no div */ in rk3576_vop2_if_cfg()
3937 dclk_in_rate = mode->crtc_clock / cstate->crtc->vps[cstate->crtc_id].dclk_div; in rk3576_vop2_if_cfg()
3983 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4004 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4026 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4048 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4112 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4131 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4148 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4165 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4182 RK3576_IF_PORT_SEL_SHIFT, cstate->crtc_id, false); in rk3576_vop2_if_cfg()
4195 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3568_vop2_setup_dual_channel_if()
4242 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4255 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4264 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4273 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4284 LVDS1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4296 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4307 MIPI1_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4324 EDP0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4335 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3568_vop2_if_cfg()
4353 u32 vp_offset = (cstate->crtc_id * 0x100); in rk3562_vop2_if_cfg()
4364 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
4375 LVDS0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
4386 MIPI0_MUX_SHIFT, cstate->crtc_id, false); in rk3562_vop2_if_cfg()
4418 RGB_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
4425 HDMI0_MUX_SHIFT, cstate->crtc_id, false); in rk3528_vop2_if_cfg()
4441 u32 vp_offset = (cstate->crtc_id * 0x100); in vop2_post_color_swap()
4575 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); in vop2_dsc_enable()
4724 sprintf(vp_name, "port@%d", cstate->crtc_id); in is_extend_pll()
4756 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_mode_setup()
4778 u32 vp_offset = (cstate->crtc_id * 0x100); in vop3_mcu_bypass_mode_setup()
4802 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_send_mcu_cmd()
4850 static void vop2_dither_setup(struct vop2 *vop2, int bus_format, int crtc_id) in vop2_dither_setup() argument
4853 const struct vop2_vp_data *vp_data = &vop2_data->vp_data[crtc_id]; in vop2_dither_setup()
4854 u32 vp_offset = crtc_id * 0x100; in vop2_dither_setup()
4931 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; in rockchip_vop2_init()
4946 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_init()
4947 u32 line_flag_offset = (cstate->crtc_id * 4); in rockchip_vop2_init()
4949 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_init()
4968 cstate->crtc_id); in rockchip_vop2_init()
4972 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; in rockchip_vop2_init()
4975 __func__, cstate->crtc_id); in rockchip_vop2_init()
4984 RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
4986 RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
4988 if (vop2->data->vp_data[cstate->crtc_id].urgency) { in rockchip_vop2_init()
4989 u8 urgen_thl = vop2->data->vp_data[cstate->crtc_id].urgency->urgen_thl; in rockchip_vop2_init()
4990 u8 urgen_thh = vop2->data->vp_data[cstate->crtc_id].urgency->urgen_thh; in rockchip_vop2_init()
4993 AXI0_PORT_URGENCY_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
4995 AXI1_PORT_URGENCY_EN_SHIFT + cstate->crtc_id, 1, false); in rockchip_vop2_init()
5044 vop2_dither_setup(vop2, conn_state->bus_format, cstate->crtc_id); in rockchip_vop2_init()
5049 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
5110 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); in rockchip_vop2_init()
5146 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); in rockchip_vop2_init()
5185 vp_dclk_div = cstate->crtc->vps[cstate->crtc_id].dclk_div; in rockchip_vop2_init()
5232 __func__, cstate->crtc_id, dclk_rate, ret); in rockchip_vop2_init()
5241 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); in rockchip_vop2_init()
5554 cstate->crtc_id, false); in vop2_set_cluster_win()
5555 vop2_ops->setup_win_dly(state, cstate->crtc_id, win->phys_id); in vop2_set_cluster_win()
5652 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); in vop2_set_smart_win()
5677 cstate->crtc_id, false); in vop2_set_smart_win()
5678 vop2_ops->setup_win_dly(state, cstate->crtc_id, win->phys_id); in vop2_set_smart_win()
5681 if (vop2->version == VOP_VERSION_RK3576 && cstate->crtc_id == 0 && in vop2_set_smart_win()
5788 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_set_plane()
5809 printf("open vp%d plane pd fail\n", cstate->crtc_id); in rockchip_vop2_set_plane()
5840 cstate->crtc_id, vop2_plane_phys_id_to_string(primary_plane_id), in rockchip_vop2_set_plane()
5876 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_enable()
5877 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_enable()
5903 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rk3588_vop2_post_enable()
5917 val & BIT(cstate->crtc_id), 50 * 1000); in rk3588_vop2_post_enable()
5937 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rk3576_vop2_post_enable()
5955 val & BIT(cstate->crtc_id), 50 * 1000); in rk3576_vop2_post_enable()
5986 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_disable()
5987 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); in rockchip_vop2_disable()
6053 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { in rockchip_vop2_check()
6054 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); in rockchip_vop2_check()
6078 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); in rockchip_vop2_mode_valid()
6207 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; in rockchip_vop2_plane_check()
6221 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); in rockchip_vop2_plane_check()
6233 u32 vp_offset = (cstate->crtc_id * 0x100); in rockchip_vop2_apply_soft_te()
6251 cstate->crtc_id); in rockchip_vop2_apply_soft_te()
6255 printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
6260 printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id); in rockchip_vop2_apply_soft_te()
6341 static void rk3528_setup_win_dly(struct display_state *state, int crtc_id, u8 plane_phy_id) in rk3528_setup_win_dly() argument
6407 static void rk3568_setup_win_dly(struct display_state *state, int crtc_id, u8 plane_phy_id) in rk3568_setup_win_dly() argument
6516 static void rk3576_setup_win_dly(struct display_state *state, int crtc_id, u8 plane_phy_id) in rk3576_setup_win_dly() argument