3480 	unsigned long v_pixclk = mode->crtc_clock * 1000L;  in vop2_calc_cru_cfg()
3611 	u64 v_pixclk = mode->crtc_clock * 1000LL; /* video timing pixclk */  in vop2_calc_dsc_clk()
3933 	    mode->crtc_clock > VOP2_MAX_DCLK_RATE || (cstate->crtc_id == 0 && split_mode))  in rk3576_vop2_if_cfg()
3937 	dclk_in_rate = mode->crtc_clock / cstate->crtc->vps[cstate->crtc_id].dclk_div;  in rk3576_vop2_if_cfg()
3940 		dclk_core_rate = mode->crtc_clock / 2;  in rk3576_vop2_if_cfg()
3942 		dclk_core_rate = mode->crtc_clock / port_pix_rate;  in rk3576_vop2_if_cfg()
4187 	return mode->crtc_clock;  in rk3576_vop2_if_cfg()
4343 	return mode->crtc_clock;  in rk3568_vop2_if_cfg()
4400 	return mode->crtc_clock;  in rk3562_vop2_if_cfg()
4433 	return mode->crtc_clock;  in rk3528_vop2_if_cfg()
4614 		u32 v_pixclk_mhz = mode->crtc_clock / 1000; /* video timing pixclk */  in vop2_dsc_enable()
4844 		vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000);  in rockchip_vop2_send_mcu_cmd()
5187 	if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) {  in rockchip_vop2_init()
5236 			mode->crtc_clock = roundup(ret, 1000) / 1000;  in rockchip_vop2_init()
5238 			dclk_div_factor = mode->crtc_clock / dclk_rate;  in rockchip_vop2_init()
5239 			mode->crtc_clock = roundup(ret, 1000) * dclk_div_factor / 1000;  in rockchip_vop2_init()
5241 		printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock);  in rockchip_vop2_init()
6149 				mode->crtc_clock = (u32)mode->crtc_htotal * mode->crtc_vtotal *  in rockchip_vop2_mode_fixup()
6178 		mode->crtc_clock *= 2;  in rockchip_vop2_mode_fixup()
6187 		mode->crtc_clock *= 4;  in rockchip_vop2_mode_fixup()
6189 	mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(conn_state->bus_format);  in rockchip_vop2_mode_fixup()
6191 		mode->crtc_clock *= cstate->mcu_timing.mcu_pix_total + 1;  in rockchip_vop2_mode_fixup()