443 #define RK3568_VP0_MIPI_CTRL			0xC04  macro
3727 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
3729 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
3753 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
3755 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
3761 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3588_vop2_if_cfg()
3764 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3588_vop2_if_cfg()
4063 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3576_vop2_if_cfg()
4065 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3576_vop2_if_cfg()
4071 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3576_vop2_if_cfg()
4074 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3576_vop2_if_cfg()
4210 	vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3568_vop2_setup_dual_channel_if()
4213 		vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK,  in rk3568_vop2_setup_dual_channel_if()
4393 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3562_vop2_if_cfg()
4395 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rk3562_vop2_if_cfg()
5102 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rockchip_vop2_init()
5105 			vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rockchip_vop2_init()
6237 	ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val,  in rockchip_vop2_apply_soft_te()
6247 				vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,  in rockchip_vop2_apply_soft_te()