Lines Matching refs:RK3568_REG_CFG_DONE
42 #define RK3568_REG_CFG_DONE 0x000 macro
5250 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_init()
5885 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_enable()
5915 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rk3588_vop2_post_enable()
5916 ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val, in rk3588_vop2_post_enable()
5953 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rk3576_vop2_post_enable()
5954 ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val, in rk3576_vop2_post_enable()
5995 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); in rockchip_vop2_disable()
6620 writel(cfg_done, regs + RK3568_REG_CFG_DONE + offset); in vop2_vp_config_done()
6692 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
6865 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
7000 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
7250 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0, 0x200 },
7545 { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },