67 #define RK3568_DSP_IF_EN			0x028  macro
3684 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT,  in rk3588_vop2_if_cfg()
3691 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT,  in rk3588_vop2_if_cfg()
3701 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT,  in rk3588_vop2_if_cfg()
3720 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT,  in rk3588_vop2_if_cfg()
3722 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false);  in rk3588_vop2_if_cfg()
3745 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT,  in rk3588_vop2_if_cfg()
3747 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT,  in rk3588_vop2_if_cfg()
3790 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT,  in rk3588_vop2_if_cfg()
3792 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT,  in rk3588_vop2_if_cfg()
3805 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT,  in rk3588_vop2_if_cfg()
3807 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT,  in rk3588_vop2_if_cfg()
3820 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT,  in rk3588_vop2_if_cfg()
3822 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT,  in rk3588_vop2_if_cfg()
3842 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT,  in rk3588_vop2_if_cfg()
3844 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT,  in rk3588_vop2_if_cfg()
3864 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT,  in rk3588_vop2_if_cfg()
3871 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT,  in rk3588_vop2_if_cfg()
4239 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,  in rk3568_vop2_if_cfg()
4241 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4250 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,  in rk3568_vop2_if_cfg()
4252 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK,  in rk3568_vop2_if_cfg()
4254 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4261 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,  in rk3568_vop2_if_cfg()
4263 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4270 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,  in rk3568_vop2_if_cfg()
4272 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4281 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT,  in rk3568_vop2_if_cfg()
4283 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4293 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,  in rk3568_vop2_if_cfg()
4295 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4304 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT,  in rk3568_vop2_if_cfg()
4306 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4321 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT,  in rk3568_vop2_if_cfg()
4323 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4332 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,  in rk3568_vop2_if_cfg()
4334 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3568_vop2_if_cfg()
4361 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,  in rk3562_vop2_if_cfg()
4363 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3562_vop2_if_cfg()
4372 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,  in rk3562_vop2_if_cfg()
4374 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3562_vop2_if_cfg()
4383 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,  in rk3562_vop2_if_cfg()
4385 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3562_vop2_if_cfg()
4415 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,  in rk3528_vop2_if_cfg()
4417 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3528_vop2_if_cfg()
4422 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,  in rk3528_vop2_if_cfg()
4424 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,  in rk3528_vop2_if_cfg()
5907 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT,  in rk3588_vop2_post_enable()
5911 		vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT,  in rk3588_vop2_post_enable()