Lines Matching refs:EN_MASK
46 #define EN_MASK 1 macro
1883 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); in rk3568_vop2_load_lut()
1905 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); in rk3588_vop2_load_lut()
1907 EN_MASK, GAMMA_UPDATE_EN_SHIFT, 1, false); in rk3588_vop2_load_lut()
2024 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); in rockchip_vop2_cubic_lut_init()
2026 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); in rockchip_vop2_cubic_lut_init()
2028 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); in rockchip_vop2_cubic_lut_init()
2485 EN_MASK, PD_VOP_CLUSTER_REPAIR_ENA_SHIFT); in rk3576_vop2_wait_power_domain_on()
2487 EN_MASK, PD_VOP_CLUSTER_REPAIR_ENA_SHIFT); in rk3576_vop2_wait_power_domain_on()
2498 EN_MASK, PD_VOP_ESMART_REPAIR_ENA_SHIFT); in rk3576_vop2_wait_power_domain_on()
2500 EN_MASK, PD_VOP_ESMART_REPAIR_ENA_SHIFT); in rk3576_vop2_wait_power_domain_on()
2517 vop2_mask_write(vop2, RK3576_SYS_CLUSTER_PD_CTRL, EN_MASK, in rk3576_vop2_power_domain_on()
2520 vop2_mask_write(vop2, RK3576_SYS_ESMART_PD_CTRL, EN_MASK, in rk3576_vop2_power_domain_on()
2549 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); in rk3588_vop2_wait_power_domain_on()
2567 vop2_mask_write(vop2, RK3588_SYS_PD_CTRL, EN_MASK, in rk3588_vop2_power_domain_on()
3039 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, in vop2_global_initial()
3083 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, in vop2_global_initial()
3085 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in vop2_global_initial()
3131 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, in vop2_global_initial()
3134 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK, in vop2_global_initial()
3150 vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK, in vop2_global_initial()
3161 vop2_mask_write(vop2, RK3576_SYS_MMU_CTRL, EN_MASK, RKMMU_V2_EN_SHIFT, 1, true); in vop2_global_initial()
3172 vop2_mask_write(vop2, RK3576_SYS_PORT_CTRL, EN_MASK, in vop2_global_initial()
3686 vop2_grf_writel(vop2, vop2->grf, RK3588_GRF_SOC_CON1, EN_MASK, in rk3588_vop2_if_cfg()
3693 vop2_grf_writel(vop2, vop2->grf, RK3588_GRF_SOC_CON1, EN_MASK, in rk3588_vop2_if_cfg()
3696 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, RK3588_BT1120_YC_SWAP_SHIFT, in rk3588_vop2_if_cfg()
3703 vop2_grf_writel(vop2, vop2->grf, RK3588_GRF_SOC_CON1, EN_MASK, in rk3588_vop2_if_cfg()
3706 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, RK3588_BT656_YC_SWAP_SHIFT, in rk3588_vop2_if_cfg()
3717 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3720 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, in rk3588_vop2_if_cfg()
3728 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3588_vop2_if_cfg()
3730 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); in rk3588_vop2_if_cfg()
3742 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3745 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, in rk3588_vop2_if_cfg()
3754 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3588_vop2_if_cfg()
3756 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); in rk3588_vop2_if_cfg()
3761 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3588_vop2_if_cfg()
3765 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, in rk3588_vop2_if_cfg()
3769 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3773 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3777 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3781 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3588_vop2_if_cfg()
3790 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, in rk3588_vop2_if_cfg()
3800 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3805 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, in rk3588_vop2_if_cfg()
3815 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3820 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, in rk3588_vop2_if_cfg()
3831 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3834 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3842 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, in rk3588_vop2_if_cfg()
3853 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3856 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, in rk3588_vop2_if_cfg()
3965 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3968 vop2_mask_write(vop2, RK3568_VP0_DCLK_SEL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
3976 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3978 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3980 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3986 vop2_grf_writel(vop2, vop2->ioc_grf, RK3576_VCCIO_IOC_MISC_CON8, EN_MASK, in rk3576_vop2_if_cfg()
3995 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3997 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
3999 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4001 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4005 vop2_grf_writel(vop2, vop2->ioc_grf, RK3576_VCCIO_IOC_MISC_CON8, EN_MASK, in rk3576_vop2_if_cfg()
4008 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4017 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4019 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4021 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4023 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4027 vop2_grf_writel(vop2, vop2->ioc_grf, RK3576_VCCIO_IOC_MISC_CON8, EN_MASK, in rk3576_vop2_if_cfg()
4030 vop2_mask_write(vop2, RK3576_RGB_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4041 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4043 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4045 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4059 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4063 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4065 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4071 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4074 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3576_vop2_if_cfg()
4078 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4082 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4086 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4090 vop2_mask_write(vop2, RK3576_MIPI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4105 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4107 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4109 vop2_mask_write(vop2, RK3576_EDP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4124 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4126 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4128 vop2_mask_write(vop2, RK3576_HDMI0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4143 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4145 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4160 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4162 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4177 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4179 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_if_cfg()
4199 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4201 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4204 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4210 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4213 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4218 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4220 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, in rk3568_vop2_setup_dual_channel_if()
4239 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
4245 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
4250 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3568_vop2_if_cfg()
4252 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, in rk3568_vop2_if_cfg()
4256 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
4261 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3568_vop2_if_cfg()
4265 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, in rk3568_vop2_if_cfg()
4270 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3568_vop2_if_cfg()
4276 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4281 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, in rk3568_vop2_if_cfg()
4287 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4293 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3568_vop2_if_cfg()
4297 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4304 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, in rk3568_vop2_if_cfg()
4308 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4321 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, in rk3568_vop2_if_cfg()
4325 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4332 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3568_vop2_if_cfg()
4336 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3568_vop2_if_cfg()
4361 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, in rk3562_vop2_if_cfg()
4365 vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK, in rk3562_vop2_if_cfg()
4372 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, in rk3562_vop2_if_cfg()
4376 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
4383 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, in rk3562_vop2_if_cfg()
4387 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3562_vop2_if_cfg()
4394 EN_MASK, EDPI_TE_EN, !cstate->soft_te, false); in rk3562_vop2_if_cfg()
4396 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); in rk3562_vop2_if_cfg()
4415 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, in rk3528_vop2_if_cfg()
4422 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, in rk3528_vop2_if_cfg()
4426 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, in rk3528_vop2_if_cfg()
4572 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
4605 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, in vop2_dsc_enable()
4758 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4760 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
4780 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4782 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
4815 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4820 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4824 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4831 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_send_mcu_cmd()
4860 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4862 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4870 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4872 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4887 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4897 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4913 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4916 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4921 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in vop2_dither_setup()
4979 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, in rockchip_vop2_init()
4983 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
4985 vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK, in rockchip_vop2_init()
4992 vop2_mask_write(vop2, RK3576_SYS_AXI_HURRY_CTRL0_IMD, EN_MASK, in rockchip_vop2_init()
4994 vop2_mask_write(vop2, RK3576_SYS_AXI_HURRY_CTRL1_IMD, EN_MASK, in rockchip_vop2_init()
4996 vop2_mask_write(vop2, RK3568_VP0_COLOR_BAR_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5049 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, in rockchip_vop2_init()
5072 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5074 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5076 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5081 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5083 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5095 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5098 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5124 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5128 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5251 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_init()
5372 EN_MASK, WIN0_ZME_DERING_EN_SHIFT, zme_dering_en, false); in vop2_setup_scale()
5385 EN_MASK, CLUSTER_XGT_EN_SHIFT, xgt_en, false); in vop2_setup_scale()
5387 EN_MASK, CLUSTER_XAVG_EN_SHIFT, xavg_en, false); in vop2_setup_scale()
5431 EN_MASK, ESMART_XGT_EN_SHIFT, xgt_en, false); in vop2_setup_scale()
5433 EN_MASK, ESMART_XAVG_EN_SHIFT, xavg_en, false); in vop2_setup_scale()
5563 EN_MASK, CLUSTER_AFBCD_HALF_BLOCK_SHIFT, 1, false); in vop2_set_cluster_win()
5580 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
5587 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, in vop2_set_cluster_win()
5590 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); in vop2_set_cluster_win()
5591 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); in vop2_set_cluster_win()
5696 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, in vop2_set_smart_win()
5721 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, in vop2_set_smart_win()
5728 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
5731 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, in vop2_set_smart_win()
5862 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, in vop2_dsc_cfg_done()
5864 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, in vop2_dsc_cfg_done()
5867 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, in vop2_dsc_cfg_done()
5879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5891 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in rockchip_vop2_enable()
5907 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, in rk3588_vop2_post_enable()
5911 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, in rk3588_vop2_post_enable()
5941 vop2_mask_write(vop2, RK3576_DP0_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5945 vop2_mask_write(vop2, RK3576_DP1_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5949 vop2_mask_write(vop2, RK3576_DP2_IF_CTRL, EN_MASK, in rk3576_vop2_post_enable()
5989 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, in rockchip_vop2_disable()
6248 EN_MASK, EDPI_WMS_FS, 1, false); in rockchip_vop2_apply_soft_te()