1917 	int i, lut_len, ret = 0;  in rockchip_vop2_gamma_lut_init()  local
1928 	ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res);  in rockchip_vop2_gamma_lut_init()
1929 	if (ret)  in rockchip_vop2_gamma_lut_init()
2514 	int ret = 0;  in rk3576_vop2_power_domain_on()  local
2522 	ret = rk3576_vop2_wait_power_domain_on(vop2, pd_data);  in rk3576_vop2_power_domain_on()
2523 	if (ret) {  in rk3576_vop2_power_domain_on()
2525 		return ret;  in rk3576_vop2_power_domain_on()
2565 	int ret = 0;  in rk3588_vop2_power_domain_on()  local
2569 	ret = rk3588_vop2_wait_power_domain_on(vop2, pd_data);  in rk3588_vop2_power_domain_on()
2570 	if (ret) {  in rk3588_vop2_power_domain_on()
2572 		return ret;  in rk3588_vop2_power_domain_on()
2581 	int ret = 0;  in vop2_power_domain_on()  local
2593 		ret = vop2_power_domain_on(vop2, pd_data->parent_id);  in vop2_power_domain_on()
2594 		if (ret) {  in vop2_power_domain_on()
2607 		ret = rk3576_vop2_power_domain_on(vop2, pd_data);  in vop2_power_domain_on()
2609 		ret = rk3588_vop2_power_domain_on(vop2, pd_data);  in vop2_power_domain_on()
2611 	return ret;  in vop2_power_domain_on()
3190 	int ret;  in rockchip_vop2_sharp_init()  local
3195 	ret = ofnode_read_resource_byname(cstate->node, "sharp_regs", &sharp_regs);  in rockchip_vop2_sharp_init()
3196 	if (ret) {  in rockchip_vop2_sharp_init()
3217 	int ret;  in rockchip_vop2_acm_init()  local
3222 	ret = ofnode_read_resource_byname(cstate->node, "acm_regs", &acm_regs);  in rockchip_vop2_acm_init()
3223 	if (ret) {  in rockchip_vop2_acm_init()
3252 	int ret = 0;  in rockchip_vop2_of_get_gamma_lut()  local
3258 	ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res);  in rockchip_vop2_of_get_gamma_lut()
3259 	if (ret)  in rockchip_vop2_of_get_gamma_lut()
3281 		ret = of_read_u32_array(dsp_lut_node, "gamma-lut", lut, length);  in rockchip_vop2_of_get_gamma_lut()
3282 		if (ret) {  in rockchip_vop2_of_get_gamma_lut()
3315 	int ret = 0;  in rockchip_vop2_of_get_dsp_lut()  local
3325 	ret = rockchip_vop2_of_get_gamma_lut(state, dsp_lut_node);  in rockchip_vop2_of_get_dsp_lut()
3326 	if (ret)  in rockchip_vop2_of_get_dsp_lut()
3356 	int ret;  in rockchip_vop2_preinit()  local
3405 		ret = power_domain_get(cstate->dev, &pwrdom);  in rockchip_vop2_preinit()
3406 		if (ret) {  in rockchip_vop2_preinit()
3407 			printf("failed to get pwrdom: %d\n", ret);  in rockchip_vop2_preinit()
3408 			return ret;  in rockchip_vop2_preinit()
3410 		ret = power_domain_on(&pwrdom);  in rockchip_vop2_preinit()
3411 		if (ret) {  in rockchip_vop2_preinit()
3412 			printf("failed to power on pd: %d\n", ret);  in rockchip_vop2_preinit()
3413 			return ret;  in rockchip_vop2_preinit()
3415 		ret = clk_get_bulk(cstate->dev, &clks);  in rockchip_vop2_preinit()
3416 		if (ret) {  in rockchip_vop2_preinit()
3417 			if (ret != -ENOSYS && ret != -ENOENT) {  in rockchip_vop2_preinit()
3418 				printf("failed to get clk: %d\n", ret);  in rockchip_vop2_preinit()
3419 				return ret;  in rockchip_vop2_preinit()
3422 		ret = clk_enable_bulk(&clks);  in rockchip_vop2_preinit()
3423 		if (ret) {  in rockchip_vop2_preinit()
3424 			printf("failed to enable clk: %d\n", ret);  in rockchip_vop2_preinit()
3426 			return ret;  in rockchip_vop2_preinit()
3433 		ret = reset_get_by_name(cstate->dev, dclk_name, &cstate->dclk_rst);  in rockchip_vop2_preinit()
3434 		if (ret < 0) {  in rockchip_vop2_preinit()
3435 			printf("%s: failed to get dclk reset: %d\n", __func__, ret);  in rockchip_vop2_preinit()
4463 	int ret = 0;  in vop2_clk_set_parent()  local
4466 		ret = clk_set_parent(clk, parent);  in vop2_clk_set_parent()
4467 	if (ret < 0)  in vop2_clk_set_parent()
4475 	int ret = 0;  in vop2_clk_set_rate()  local
4478 		ret = clk_set_rate(clk, rate);  in vop2_clk_set_rate()
4479 	if (ret < 0)  in vop2_clk_set_rate()
4482 	return ret;  in vop2_clk_set_rate()
4719 	int ret;  in is_extend_pll()  local
4730 	ret = dev_read_phandle_with_args(vp_dev, "assigned-clock-parents", "#clock-cells", 0,  in is_extend_pll()
4732 	if (ret) {  in is_extend_pll()
4961 	int ret;  in rockchip_vop2_init()  local
5147 	ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk);  in rockchip_vop2_init()
5148 	if (ret) {  in rockchip_vop2_init()
5149 		printf("%s: Failed to get dclk ret=%d\n", __func__, ret);  in rockchip_vop2_init()
5150 		return ret;  in rockchip_vop2_init()
5154 	ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev);  in rockchip_vop2_init()
5155 	if (!ret) {  in rockchip_vop2_init()
5156 		ret = clk_get_by_name(disp_dev, "hdmi0_phy_pll", &hdmi0_phy_pll);  in rockchip_vop2_init()
5157 		if (ret)  in rockchip_vop2_init()
5159 		ret = clk_get_by_name(disp_dev, "hdmi1_phy_pll", &hdmi1_phy_pll);  in rockchip_vop2_init()
5160 		if (ret)  in rockchip_vop2_init()
5171 		ret = dev_read_phandle_with_args(cstate->dev, "assigned-clock-parents",  in rockchip_vop2_init()
5173 		if (!ret) {  in rockchip_vop2_init()
5174 			ret = uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &hdmi0_phy_pll.dev);  in rockchip_vop2_init()
5175 			if (ret) {  in rockchip_vop2_init()
5177 				return ret;  in rockchip_vop2_init()
5200 			ret = vop2_clk_set_rate(&hdmi0_phy_pll, dclk_rate / vp_dclk_div * 1000);  in rockchip_vop2_init()
5202 			ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate / vp_dclk_div * 1000);  in rockchip_vop2_init()
5205 				ret = vop2_clk_set_rate(&hdmi_phy_pll,  in rockchip_vop2_init()
5209 				ret = vop2_clk_set_rate(&cstate->dclk,  in rockchip_vop2_init()
5218 					ret = dclk_rate * 1000;  in rockchip_vop2_init()
5225 			ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate / vp_dclk_div * 1000);  in rockchip_vop2_init()
5227 			ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate / vp_dclk_div * 1000);  in rockchip_vop2_init()
5230 	if (IS_ERR_VALUE(ret)) {  in rockchip_vop2_init()
5232 		       __func__, cstate->crtc_id, dclk_rate, ret);  in rockchip_vop2_init()
5233 		return ret;  in rockchip_vop2_init()
5236 			mode->crtc_clock = roundup(ret, 1000) / 1000;  in rockchip_vop2_init()
5239 			mode->crtc_clock = roundup(ret, 1000) * dclk_div_factor / 1000;  in rockchip_vop2_init()
5789 	int ret;  in rockchip_vop2_set_plane()  local
5833 		ret = vop2_set_cluster_win(state, win_data);  in rockchip_vop2_set_plane()
5835 		ret = vop2_set_smart_win(state, win_data);  in rockchip_vop2_set_plane()
5836 	if (ret)  in rockchip_vop2_set_plane()
5837 		return ret;  in rockchip_vop2_set_plane()
5904 	int ret, val;  in rk3588_vop2_post_enable()  local
5916 		ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val,  in rk3588_vop2_post_enable()
5918 		if (ret)  in rk3588_vop2_post_enable()
5938 	int ret, val;  in rk3576_vop2_post_enable()  local
5954 		ret = readl_poll_timeout(vop2->regs + RK3568_REG_CFG_DONE, val,  in rk3576_vop2_post_enable()
5956 		if (ret)  in rk3576_vop2_post_enable()
6235 	int ret = 0;  in rockchip_vop2_apply_soft_te()  local
6237 	ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val,  in rockchip_vop2_apply_soft_te()
6239 	if (!ret) {  in rockchip_vop2_apply_soft_te()
6241 		ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,  in rockchip_vop2_apply_soft_te()
6243 		if (!ret) {  in rockchip_vop2_apply_soft_te()
6244 			ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,  in rockchip_vop2_apply_soft_te()
6246 			if (!ret) {  in rockchip_vop2_apply_soft_te()
6252 				return ret;  in rockchip_vop2_apply_soft_te()
6256 			return ret;  in rockchip_vop2_apply_soft_te()
6261 		return ret;  in rockchip_vop2_apply_soft_te()