306 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val)  in dsi_write()  function
324 	dsi_write(dsi2, reg, tmp);  in dsi_update_bits()
499 			dsi_write(dsi2, DSI2_CRI_TX_PLD, val);  in dw_mipi_dsi2_transfer()
503 			dsi_write(dsi2, DSI2_CRI_TX_PLD, val);  in dw_mipi_dsi2_transfer()
512 	dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val);  in dw_mipi_dsi2_transfer()
553 	dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val);  in dw_mipi_dsi2_ipi_color_coding_cfg()
574 	dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));  in dw_mipi_dsi2_ipi_set()
606 	dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time));  in dw_mipi_dsi2_ipi_set()
610 	dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time));  in dw_mipi_dsi2_ipi_set()
614 	dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time));  in dw_mipi_dsi2_ipi_set()
618 	dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time));  in dw_mipi_dsi2_ipi_set()
620 	dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa));  in dw_mipi_dsi2_ipi_set()
621 	dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp));  in dw_mipi_dsi2_ipi_set()
622 	dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact));  in dw_mipi_dsi2_ipi_set()
623 	dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp));  in dw_mipi_dsi2_ipi_set()
647 	dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val);  in dw_mipi_dsi2_set_vid_mode()
649 	dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE);  in dw_mipi_dsi2_set_vid_mode()
662 	dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE);  in dw_mipi_dsi2_set_data_stream_mode()
675 	dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE);  in dw_mipi_dsi2_set_cmd_mode()
694 		dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE);  in dw_mipi_dsi2_enable()
715 	dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0);  in dw_mipi_dsi2_disable()
727 	dsi_write(dsi2, DSI2_PWR_UP, RESET);  in dw_mipi_dsi2_post_disable()
988 	dsi_write(dsi2, DSI2_SOFT_RESET, 0X0);  in dw_mipi_dsi2_host_softrst()
990 	dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN);  in dw_mipi_dsi2_host_softrst()
1001 	dsi_write(dsi2, MANUAL_MODE_CFG, mode);  in dw_mipi_dsi2_work_mode()
1011 	dsi_write(dsi2, DSI2_PHY_MODE_CFG, val);  in dw_mipi_dsi2_phy_mode_cfg()
1030 	dsi_write(dsi2, DSI2_PHY_CLK_CFG, val);  in dw_mipi_dsi2_phy_clk_mode_cfg()
1053 	dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp));  in dw_mipi_dsi2_phy_ratio_cfg()
1057 	dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp));  in dw_mipi_dsi2_phy_ratio_cfg()
1074 	dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp));  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1079 	dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp));  in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1105 	dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val);  in dw_mipi_dsi2_tx_option_set()
1106 	dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel));  in dw_mipi_dsi2_tx_option_set()
1109 		dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN);  in dw_mipi_dsi2_tx_option_set()
1115 		dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1);  in dw_mipi_dsi2_irq_enable()
1116 		dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf);  in dw_mipi_dsi2_irq_enable()
1117 		dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1);  in dw_mipi_dsi2_irq_enable()
1118 		dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1);  in dw_mipi_dsi2_irq_enable()
1119 		dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1);  in dw_mipi_dsi2_irq_enable()
1120 		dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1);  in dw_mipi_dsi2_irq_enable()
1121 		dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1);  in dw_mipi_dsi2_irq_enable()
1123 		dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0);  in dw_mipi_dsi2_irq_enable()
1124 		dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0);  in dw_mipi_dsi2_irq_enable()
1125 		dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0);  in dw_mipi_dsi2_irq_enable()
1126 		dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0);  in dw_mipi_dsi2_irq_enable()
1127 		dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0);  in dw_mipi_dsi2_irq_enable()
1128 		dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0);  in dw_mipi_dsi2_irq_enable()
1129 		dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0);  in dw_mipi_dsi2_irq_enable()
1147 	dsi_write(dsi2, DSI2_PWR_UP, RESET);  in dw_mipi_dsi2_pre_enable()
1154 	dsi_write(dsi2, DSI2_PWR_UP, POWER_UP);  in dw_mipi_dsi2_pre_enable()