Lines Matching refs:dsi2
306 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) in dsi_write() argument
308 writel(val, dsi2->base + reg); in dsi_write()
311 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) in dsi_read() argument
313 return readl(dsi2->base + reg); in dsi_read()
316 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, in dsi_update_bits() argument
321 orig = dsi_read(dsi2, reg); in dsi_update_bits()
324 dsi_write(dsi2, reg, tmp); in dsi_update_bits()
327 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, in grf_field_write() argument
330 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : in grf_field_write()
331 dsi2->pdata->dsi0_grf_reg_fields[index]; in grf_field_write()
342 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); in grf_field_write()
345 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_get_lane_rate() argument
347 const struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_get_lane_rate()
353 max_lane_rate = (dsi2->c_option) ? in dw_mipi_dsi2_get_lane_rate()
354 dsi2->pdata->cphy_max_symbol_rate_per_lane : in dw_mipi_dsi2_get_lane_rate()
355 dsi2->pdata->dphy_max_bit_rate_per_lane; in dw_mipi_dsi2_get_lane_rate()
361 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); in dw_mipi_dsi2_get_lane_rate()
367 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); in dw_mipi_dsi2_get_lane_rate()
371 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; in dw_mipi_dsi2_get_lane_rate()
375 if (dsi2->c_option) in dw_mipi_dsi2_get_lane_rate()
383 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { in dw_mipi_dsi2_get_lane_rate()
396 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) in cri_fifos_wait_avail() argument
402 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, in cri_fifos_wait_avail()
413 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_read_from_fifo() argument
420 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); in dw_mipi_dsi2_read_from_fifo()
423 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, in dw_mipi_dsi2_read_from_fifo()
431 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); in dw_mipi_dsi2_read_from_fifo()
444 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); in dw_mipi_dsi2_read_from_fifo()
452 static void dw_mipi_dsi2_clk_management(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_clk_management() argument
460 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) in dw_mipi_dsi2_clk_management()
465 dsi_update_bits(dsi2, DSI2_PHY_CLK_CFG, CLK_TYPE_MASK, clk_type); in dw_mipi_dsi2_clk_management()
468 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_transfer() argument
476 dw_mipi_dsi2_clk_management(dsi2); in dw_mipi_dsi2_transfer()
477 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, in dw_mipi_dsi2_transfer()
489 ret = cri_fifos_wait_avail(dsi2); in dw_mipi_dsi2_transfer()
499 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); in dw_mipi_dsi2_transfer()
503 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); in dw_mipi_dsi2_transfer()
512 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); in dw_mipi_dsi2_transfer()
514 ret = cri_fifos_wait_avail(dsi2); in dw_mipi_dsi2_transfer()
519 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); in dw_mipi_dsi2_transfer()
524 if (dsi2->slave) { in dw_mipi_dsi2_transfer()
525 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); in dw_mipi_dsi2_transfer()
533 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_ipi_color_coding_cfg() argument
537 switch (dsi2->format) { in dw_mipi_dsi2_ipi_color_coding_cfg()
552 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); in dw_mipi_dsi2_ipi_color_coding_cfg()
553 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); in dw_mipi_dsi2_ipi_color_coding_cfg()
554 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); in dw_mipi_dsi2_ipi_color_coding_cfg()
556 if (dsi2->dsc_enable) in dw_mipi_dsi2_ipi_color_coding_cfg()
557 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); in dw_mipi_dsi2_ipi_color_coding_cfg()
560 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_ipi_set() argument
562 struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_ipi_set()
569 if (dsi2->slave || dsi2->master) in dw_mipi_dsi2_ipi_set()
574 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); in dw_mipi_dsi2_ipi_set()
576 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); in dw_mipi_dsi2_ipi_set()
578 if (dsi2->auto_calc_mode) in dw_mipi_dsi2_ipi_set()
585 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) in dw_mipi_dsi2_ipi_set()
599 if (dsi2->c_option) in dw_mipi_dsi2_ipi_set()
600 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); in dw_mipi_dsi2_ipi_set()
602 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); in dw_mipi_dsi2_ipi_set()
606 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); in dw_mipi_dsi2_ipi_set()
610 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); in dw_mipi_dsi2_ipi_set()
614 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); in dw_mipi_dsi2_ipi_set()
618 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); in dw_mipi_dsi2_ipi_set()
620 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); in dw_mipi_dsi2_ipi_set()
621 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); in dw_mipi_dsi2_ipi_set()
622 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); in dw_mipi_dsi2_ipi_set()
623 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); in dw_mipi_dsi2_ipi_set()
626 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_vid_mode() argument
631 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) in dw_mipi_dsi2_set_vid_mode()
634 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) in dw_mipi_dsi2_set_vid_mode()
637 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) in dw_mipi_dsi2_set_vid_mode()
640 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) in dw_mipi_dsi2_set_vid_mode()
642 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in dw_mipi_dsi2_set_vid_mode()
647 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); in dw_mipi_dsi2_set_vid_mode()
649 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); in dw_mipi_dsi2_set_vid_mode()
650 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, in dw_mipi_dsi2_set_vid_mode()
657 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_data_stream_mode() argument
662 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); in dw_mipi_dsi2_set_data_stream_mode()
663 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, in dw_mipi_dsi2_set_data_stream_mode()
670 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_cmd_mode() argument
675 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); in dw_mipi_dsi2_set_cmd_mode()
676 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, in dw_mipi_dsi2_set_cmd_mode()
683 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_enable() argument
688 dw_mipi_dsi2_clk_management(dsi2); in dw_mipi_dsi2_enable()
689 dw_mipi_dsi2_ipi_set(dsi2); in dw_mipi_dsi2_enable()
691 if (dsi2->auto_calc_mode) { in dw_mipi_dsi2_enable()
692 dsi_update_bits(dsi2, DSI2_DSI_GENERAL_CFG, BTA_EN, 0); in dw_mipi_dsi2_enable()
694 dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); in dw_mipi_dsi2_enable()
695 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, in dw_mipi_dsi2_enable()
701 dsi_update_bits(dsi2, DSI2_DSI_GENERAL_CFG, BTA_EN, BTA_EN); in dw_mipi_dsi2_enable()
704 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) in dw_mipi_dsi2_enable()
705 dw_mipi_dsi2_set_vid_mode(dsi2); in dw_mipi_dsi2_enable()
707 dw_mipi_dsi2_set_data_stream_mode(dsi2); in dw_mipi_dsi2_enable()
709 if (dsi2->slave) in dw_mipi_dsi2_enable()
710 dw_mipi_dsi2_enable(dsi2->slave); in dw_mipi_dsi2_enable()
713 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_disable() argument
715 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); in dw_mipi_dsi2_disable()
716 dw_mipi_dsi2_set_cmd_mode(dsi2); in dw_mipi_dsi2_disable()
718 if (dsi2->slave) in dw_mipi_dsi2_disable()
719 dw_mipi_dsi2_disable(dsi2->slave); in dw_mipi_dsi2_disable()
722 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_post_disable() argument
724 if (!dsi2->prepared) in dw_mipi_dsi2_post_disable()
727 dsi_write(dsi2, DSI2_PWR_UP, RESET); in dw_mipi_dsi2_post_disable()
729 if (dsi2->dcphy.phy) in dw_mipi_dsi2_post_disable()
730 rockchip_phy_power_off(dsi2->dcphy.phy); in dw_mipi_dsi2_post_disable()
732 dsi2->prepared = false; in dw_mipi_dsi2_post_disable()
734 if (dsi2->slave) in dw_mipi_dsi2_post_disable()
735 dw_mipi_dsi2_post_disable(dsi2->slave); in dw_mipi_dsi2_post_disable()
742 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_pre_init() local
743 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); in dw_mipi_dsi2_connector_pre_init()
763 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_get_dsc_params_from_sink() argument
765 struct udevice *dev = dsi2->device->dev; in dw_mipi_dsi2_get_dsc_params_from_sink()
772 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); in dw_mipi_dsi2_get_dsc_params_from_sink()
773 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); in dw_mipi_dsi2_get_dsc_params_from_sink()
774 dsi2->dsc_enable = dsi2->pdata->dsc ? in dw_mipi_dsi2_get_dsc_params_from_sink()
777 if (dsi2->slave) { in dw_mipi_dsi2_get_dsc_params_from_sink()
778 dsi2->slave->c_option = dsi2->c_option; in dw_mipi_dsi2_get_dsc_params_from_sink()
779 dsi2->slave->scrambling_en = dsi2->scrambling_en; in dw_mipi_dsi2_get_dsc_params_from_sink()
780 dsi2->slave->dsc_enable = dsi2->dsc_enable; in dw_mipi_dsi2_get_dsc_params_from_sink()
783 if (!dsi2->dsc_enable) in dw_mipi_dsi2_get_dsc_params_from_sink()
786 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); in dw_mipi_dsi2_get_dsc_params_from_sink()
787 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); in dw_mipi_dsi2_get_dsc_params_from_sink()
788 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); in dw_mipi_dsi2_get_dsc_params_from_sink()
789 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); in dw_mipi_dsi2_get_dsc_params_from_sink()
822 dsi2->pps = pps; in dw_mipi_dsi2_get_dsc_params_from_sink()
824 if (dsi2->slave) { in dw_mipi_dsi2_get_dsc_params_from_sink()
827 dsi2->pps->pic_width = cpu_to_be16(pic_width); in dw_mipi_dsi2_get_dsc_params_from_sink()
838 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_init() local
844 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); in dw_mipi_dsi2_connector_init()
845 dsi2->dcphy.phy = conn->phy; in dw_mipi_dsi2_connector_init()
851 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; in dw_mipi_dsi2_connector_init()
853 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { in dw_mipi_dsi2_connector_init()
855 conn_state->hold_mode = dsi2->disable_hold_mode ? false : true; in dw_mipi_dsi2_connector_init()
858 if (dsi2->dual_channel) { in dw_mipi_dsi2_connector_init()
865 dsi2->slave = dev_get_priv(dev); in dw_mipi_dsi2_connector_init()
866 if (!dsi2->slave) in dw_mipi_dsi2_connector_init()
869 dsi2->slave->master = dsi2; in dw_mipi_dsi2_connector_init()
870 dsi2->lanes /= 2; in dw_mipi_dsi2_connector_init()
872 dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; in dw_mipi_dsi2_connector_init()
873 dsi2->slave->lanes = dsi2->lanes; in dw_mipi_dsi2_connector_init()
874 dsi2->slave->format = dsi2->format; in dw_mipi_dsi2_connector_init()
875 dsi2->slave->mode_flags = dsi2->mode_flags; in dw_mipi_dsi2_connector_init()
876 dsi2->slave->channel = dsi2->channel; in dw_mipi_dsi2_connector_init()
879 if (dsi2->data_swap) in dw_mipi_dsi2_connector_init()
893 dsi2->slave->dcphy.phy = phy; in dw_mipi_dsi2_connector_init()
898 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); in dw_mipi_dsi2_connector_init()
900 if (dm_gpio_is_valid(&dsi2->te_gpio)) { in dw_mipi_dsi2_connector_init()
902 conn_state->te_gpio = &dsi2->te_gpio; in dw_mipi_dsi2_connector_init()
905 if (dsi2->dsc_enable) { in dw_mipi_dsi2_connector_init()
907 cstate->dsc_sink_cap.version_major = dsi2->version_major; in dw_mipi_dsi2_connector_init()
908 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; in dw_mipi_dsi2_connector_init()
909 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; in dw_mipi_dsi2_connector_init()
910 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; in dw_mipi_dsi2_connector_init()
914 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); in dw_mipi_dsi2_connector_init()
975 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) in dw_mipi_dsi2_set_hs_clk() argument
977 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); in dw_mipi_dsi2_set_hs_clk()
979 if (!dsi2->c_option) in dw_mipi_dsi2_set_hs_clk()
980 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi2_set_hs_clk()
982 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); in dw_mipi_dsi2_set_hs_clk()
983 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); in dw_mipi_dsi2_set_hs_clk()
986 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_host_softrst() argument
988 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); in dw_mipi_dsi2_host_softrst()
990 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); in dw_mipi_dsi2_host_softrst()
994 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) in dw_mipi_dsi2_work_mode() argument
1001 dsi_write(dsi2, MANUAL_MODE_CFG, mode); in dw_mipi_dsi2_work_mode()
1004 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_mode_cfg() argument
1009 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
1010 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); in dw_mipi_dsi2_phy_mode_cfg()
1011 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); in dw_mipi_dsi2_phy_mode_cfg()
1014 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_clk_mode_cfg() argument
1016 u32 sys_clk = clk_get_rate(&dsi2->sys_clk) / USEC_PER_SEC; in dw_mipi_dsi2_phy_clk_mode_cfg()
1030 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); in dw_mipi_dsi2_phy_clk_mode_cfg()
1033 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_ratio_cfg() argument
1036 u32 sys_clk = clk_get_rate(&dsi2->sys_clk); in dw_mipi_dsi2_phy_ratio_cfg()
1043 if (dsi2->c_option) in dw_mipi_dsi2_phy_ratio_cfg()
1044 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); in dw_mipi_dsi2_phy_ratio_cfg()
1047 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); in dw_mipi_dsi2_phy_ratio_cfg()
1050 ipi_clk = dsi2->mipi_pixel_rate; in dw_mipi_dsi2_phy_ratio_cfg()
1053 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); in dw_mipi_dsi2_phy_ratio_cfg()
1057 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); in dw_mipi_dsi2_phy_ratio_cfg()
1060 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg() argument
1062 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1066 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1074 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1079 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
1082 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_init() argument
1084 dw_mipi_dsi2_phy_mode_cfg(dsi2); in dw_mipi_dsi2_phy_init()
1085 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); in dw_mipi_dsi2_phy_init()
1087 if (dsi2->auto_calc_mode) in dw_mipi_dsi2_phy_init()
1090 dw_mipi_dsi2_phy_ratio_cfg(dsi2); in dw_mipi_dsi2_phy_init()
1091 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); in dw_mipi_dsi2_phy_init()
1096 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_tx_option_set() argument
1102 if (dsi2->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) in dw_mipi_dsi2_tx_option_set()
1105 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); in dw_mipi_dsi2_tx_option_set()
1106 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); in dw_mipi_dsi2_tx_option_set()
1108 if (dsi2->scrambling_en) in dw_mipi_dsi2_tx_option_set()
1109 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); in dw_mipi_dsi2_tx_option_set()
1112 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) in dw_mipi_dsi2_irq_enable() argument
1115 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); in dw_mipi_dsi2_irq_enable()
1116 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); in dw_mipi_dsi2_irq_enable()
1117 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); in dw_mipi_dsi2_irq_enable()
1118 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); in dw_mipi_dsi2_irq_enable()
1119 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); in dw_mipi_dsi2_irq_enable()
1120 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); in dw_mipi_dsi2_irq_enable()
1121 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); in dw_mipi_dsi2_irq_enable()
1123 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); in dw_mipi_dsi2_irq_enable()
1124 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); in dw_mipi_dsi2_irq_enable()
1125 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); in dw_mipi_dsi2_irq_enable()
1126 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); in dw_mipi_dsi2_irq_enable()
1127 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); in dw_mipi_dsi2_irq_enable()
1128 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); in dw_mipi_dsi2_irq_enable()
1129 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); in dw_mipi_dsi2_irq_enable()
1133 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) in mipi_dcphy_power_on() argument
1135 if (!dsi2->dcphy.phy) in mipi_dcphy_power_on()
1138 rockchip_phy_power_on(dsi2->dcphy.phy); in mipi_dcphy_power_on()
1141 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_pre_enable() argument
1143 if (dsi2->prepared) in dw_mipi_dsi2_pre_enable()
1146 dw_mipi_dsi2_host_softrst(dsi2); in dw_mipi_dsi2_pre_enable()
1147 dsi_write(dsi2, DSI2_PWR_UP, RESET); in dw_mipi_dsi2_pre_enable()
1149 dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN); in dw_mipi_dsi2_pre_enable()
1150 dw_mipi_dsi2_phy_init(dsi2); in dw_mipi_dsi2_pre_enable()
1151 dw_mipi_dsi2_tx_option_set(dsi2); in dw_mipi_dsi2_pre_enable()
1152 dw_mipi_dsi2_irq_enable(dsi2, 0); in dw_mipi_dsi2_pre_enable()
1153 mipi_dcphy_power_on(dsi2); in dw_mipi_dsi2_pre_enable()
1154 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); in dw_mipi_dsi2_pre_enable()
1155 dw_mipi_dsi2_set_cmd_mode(dsi2); in dw_mipi_dsi2_pre_enable()
1157 dsi2->prepared = true; in dw_mipi_dsi2_pre_enable()
1159 if (dsi2->slave) in dw_mipi_dsi2_pre_enable()
1160 dw_mipi_dsi2_pre_enable(dsi2->slave); in dw_mipi_dsi2_pre_enable()
1163 static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_get_mipi_pixel_clk() argument
1166 struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_get_mipi_pixel_clk()
1167 u8 k = dsi2->slave ? 2 : 1; in dw_mipi_dsi2_get_mipi_pixel_clk()
1175 if (dsi2->dsc_enable) { in dw_mipi_dsi2_get_mipi_pixel_clk()
1176 dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2; in dw_mipi_dsi2_get_mipi_pixel_clk()
1177 if (dsi2->slave) in dw_mipi_dsi2_get_mipi_pixel_clk()
1178 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; in dw_mipi_dsi2_get_mipi_pixel_clk()
1183 dsi2->mipi_pixel_rate = (mode->crtc_clock * MSEC_PER_SEC) / (4 * k); in dw_mipi_dsi2_get_mipi_pixel_clk()
1184 if (dsi2->slave) in dw_mipi_dsi2_get_mipi_pixel_clk()
1185 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; in dw_mipi_dsi2_get_mipi_pixel_clk()
1191 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_prepare() local
1196 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); in dw_mipi_dsi2_connector_prepare()
1197 if (dsi2->slave) in dw_mipi_dsi2_connector_prepare()
1198 memcpy(&dsi2->slave->mode, &dsi2->mode, in dw_mipi_dsi2_connector_prepare()
1201 dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, cstate); in dw_mipi_dsi2_connector_prepare()
1203 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); in dw_mipi_dsi2_connector_prepare()
1204 if (dsi2->dcphy.phy) in dw_mipi_dsi2_connector_prepare()
1205 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); in dw_mipi_dsi2_connector_prepare()
1207 if (dsi2->slave && dsi2->slave->dcphy.phy) in dw_mipi_dsi2_connector_prepare()
1208 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); in dw_mipi_dsi2_connector_prepare()
1211 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", in dw_mipi_dsi2_connector_prepare()
1212 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); in dw_mipi_dsi2_connector_prepare()
1214 dw_mipi_dsi2_pre_enable(dsi2); in dw_mipi_dsi2_connector_prepare()
1222 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_unprepare() local
1224 dw_mipi_dsi2_post_disable(dsi2); in dw_mipi_dsi2_connector_unprepare()
1230 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_enable() local
1232 dw_mipi_dsi2_enable(dsi2); in dw_mipi_dsi2_connector_enable()
1240 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_disable() local
1242 dw_mipi_dsi2_disable(dsi2); in dw_mipi_dsi2_connector_disable()
1250 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); in dw_mipi_dsi2_connector_mode_valid() local
1252 u8 min_pixels = dsi2->slave ? 8 : 4; in dw_mipi_dsi2_connector_mode_valid()
1296 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); in dw_mipi_dsi2_probe() local
1302 dsi2->base = dev_read_addr_ptr(dev); in dw_mipi_dsi2_probe()
1307 dsi2->grf = syscon_get_regmap(syscon); in dw_mipi_dsi2_probe()
1308 if (!dsi2->grf) in dw_mipi_dsi2_probe()
1317 &dsi2->te_gpio, GPIOD_IS_IN); in dw_mipi_dsi2_probe()
1323 ret = clk_get_by_name(dev, "sys_clk", &dsi2->sys_clk); in dw_mipi_dsi2_probe()
1329 dsi2->dev = dev; in dw_mipi_dsi2_probe()
1330 dsi2->pdata = pdata; in dw_mipi_dsi2_probe()
1331 dsi2->id = id; in dw_mipi_dsi2_probe()
1332 dsi2->dual_channel = dev_read_bool(dsi2->dev, "rockchip,dual-channel"); in dw_mipi_dsi2_probe()
1333 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); in dw_mipi_dsi2_probe()
1334 dsi2->auto_calc_mode = dev_read_bool(dsi2->dev, "auto-calculation-mode"); in dw_mipi_dsi2_probe()
1335 dsi2->disable_hold_mode = dev_read_bool(dsi2->dev, "disable-hold-mode"); in dw_mipi_dsi2_probe()
1337 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, in dw_mipi_dsi2_probe()
1399 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); in dw_mipi_dsi2_host_transfer() local
1401 return dw_mipi_dsi2_transfer(dsi2, msg); in dw_mipi_dsi2_host_transfer()
1407 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); in dw_mipi_dsi2_host_attach() local
1412 dsi2->lanes = device->lanes; in dw_mipi_dsi2_host_attach()
1413 dsi2->channel = device->channel; in dw_mipi_dsi2_host_attach()
1414 dsi2->format = device->format; in dw_mipi_dsi2_host_attach()
1415 dsi2->mode_flags = device->mode_flags; in dw_mipi_dsi2_host_attach()
1416 dsi2->device = device; in dw_mipi_dsi2_host_attach()