Lines Matching refs:drm_dp_dpcd_readb

88 	ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);  in analogix_dp_enable_rx_to_enhanced_mode()
129 		ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP,  in analogix_dp_set_enhanced_mode()
159 	ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_SET, &data);  in analogix_dp_enable_sink_to_assr_mode()
366 	drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd);  in analogix_dp_tps3_supported()
473 	retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align);  in analogix_dp_process_equalizer_training()
640 	ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data);  in analogix_dp_get_max_rx_bandwidth()
662 		ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);  in analogix_dp_get_max_rx_bandwidth()
682 	ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);  in analogix_dp_get_max_rx_lane_count()
712 	drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd);  in analogix_dp_init_training()
848 		ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,  in analogix_dp_enable_scramble()
857 		ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,  in analogix_dp_enable_scramble()
941 	ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);  in analogix_dp_link_power_up()
965 	ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);  in analogix_dp_link_power_down()