205 static int rockchip_sfc_reset(struct rockchip_sfc *sfc)  in rockchip_sfc_reset()  argument
210 	writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);  in rockchip_sfc_reset()
212 	err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,  in rockchip_sfc_reset()
216 		dev_err(sfc->dev, "SFC reset never finished\n");  in rockchip_sfc_reset()
219 	writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);  in rockchip_sfc_reset()
221 	dev_dbg(sfc->dev, "reset\n");  in rockchip_sfc_reset()
226 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)  in rockchip_sfc_get_version()  argument
228 	return  (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);  in rockchip_sfc_get_version()
231 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)  in rockchip_sfc_get_max_iosize()  argument
233 	if (sfc->version >= SFC_VER_4)  in rockchip_sfc_get_max_iosize()
239 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc)  in rockchip_sfc_get_max_dll_cells()  argument
241 	if (sfc->max_dll_cells)  in rockchip_sfc_get_max_dll_cells()
242 		return sfc->max_dll_cells;  in rockchip_sfc_get_max_dll_cells()
244 	if (sfc->version > SFC_VER_4)  in rockchip_sfc_get_max_dll_cells()
246 	else if (sfc->version == SFC_VER_4)  in rockchip_sfc_get_max_dll_cells()
252 static __maybe_unused void rockchip_sfc_set_delay_lines(struct rockchip_sfc *sfc, u16 cells, u8 cs)  in rockchip_sfc_set_delay_lines()  argument
254 	u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc);  in rockchip_sfc_set_delay_lines()
263 	writel(val, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_DLL_CTRL0);  in rockchip_sfc_set_delay_lines()
267 static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, unsigned long  speed)  in rockchip_sfc_clk_set_rate()  argument
269 	if (sfc->version < SFC_VER_8|| sfc->sclk_x2_bypass)  in rockchip_sfc_clk_set_rate()
270 		return clk_set_rate(&sfc->clk, speed);  in rockchip_sfc_clk_set_rate()
272 		return clk_set_rate(&sfc->clk, speed * 2);  in rockchip_sfc_clk_set_rate()
275 static unsigned long rockchip_sfc_clk_get_rate(struct rockchip_sfc *sfc)  in rockchip_sfc_clk_get_rate()  argument
277 	if (sfc->version < SFC_VER_8 || sfc->sclk_x2_bypass)  in rockchip_sfc_clk_get_rate()
278 		return clk_get_rate(&sfc->clk);  in rockchip_sfc_clk_get_rate()
280 		return clk_get_rate(&sfc->clk) / 2;  in rockchip_sfc_clk_get_rate()
284 static int rockchip_sfc_init(struct rockchip_sfc *sfc)  in rockchip_sfc_init()  argument
289 	printf("sfc cmd=%02xH(6BH-x4)\n", readl(sfc->regbase + SFC_CMD) & 0xFF);  in rockchip_sfc_init()
291 	writel(0, sfc->regbase + SFC_CTRL);  in rockchip_sfc_init()
292 	if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)  in rockchip_sfc_init()
293 		writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);  in rockchip_sfc_init()
294 	if (rockchip_sfc_get_version(sfc) > SFC_VER_8 && sfc->sclk_x2_bypass) {  in rockchip_sfc_init()
295 		reg = readl(sfc->regbase + SFC_EXT_CTRL);  in rockchip_sfc_init()
297 		writel(reg, sfc->regbase + SFC_EXT_CTRL);  in rockchip_sfc_init()
306 	struct rockchip_sfc *sfc = dev_get_platdata(bus);  in rockchip_cs_setup()  local
310 	ret = gpio_request_list_by_name(bus, "sfc-cs-gpios", sfc->cs_gpios,  in rockchip_cs_setup()
311 					ARRAY_SIZE(sfc->cs_gpios), 0);  in rockchip_cs_setup()
317 	for (i = 0; i < ARRAY_SIZE(sfc->cs_gpios); i++) {  in rockchip_cs_setup()
318 		if (!dm_gpio_is_valid(&sfc->cs_gpios[i]))  in rockchip_cs_setup()
321 		ret = dm_gpio_set_dir_flags(&sfc->cs_gpios[i],  in rockchip_cs_setup()
334 	struct rockchip_sfc *sfc = dev_get_platdata(bus);  in rockchip_sfc_ofdata_to_platdata()  local
336 	sfc->regbase = dev_read_addr_ptr(bus);  in rockchip_sfc_ofdata_to_platdata()
338 		sfc->use_dma = false;  in rockchip_sfc_ofdata_to_platdata()
340 		sfc->use_dma = true;  in rockchip_sfc_ofdata_to_platdata()
341 	sfc->sclk_x2_bypass = ofnode_read_bool(dev_ofnode(bus), "rockchip,sclk-x2-bypass");  in rockchip_sfc_ofdata_to_platdata()
342 	sfc->max_dll_cells = dev_read_u32_default(bus, "rockchip,max-dll", 0);  in rockchip_sfc_ofdata_to_platdata()
343 	if (sfc->max_dll_cells > SFC_DLL_CTRL0_DLL_MAX_VER5)  in rockchip_sfc_ofdata_to_platdata()
344 		sfc->max_dll_cells = SFC_DLL_CTRL0_DLL_MAX_VER5;  in rockchip_sfc_ofdata_to_platdata()
348 	ret = clk_get_by_index(bus, 0, &sfc->clk);  in rockchip_sfc_ofdata_to_platdata()
354 	ret = clk_get_by_index(bus, 1, &sfc->hclk);  in rockchip_sfc_ofdata_to_platdata()
368 	struct rockchip_sfc *sfc = dev_get_platdata(bus);  in rockchip_sfc_probe()  local
372 	ret = clk_enable(&sfc->hclk);  in rockchip_sfc_probe()
374 		dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);  in rockchip_sfc_probe()
376 	ret = clk_enable(&sfc->clk);  in rockchip_sfc_probe()
378 		dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);  in rockchip_sfc_probe()
381 	sfc->version = rockchip_sfc_get_version(sfc);  in rockchip_sfc_probe()
382 	if (sfc->version == SFC_VER_9)  in rockchip_sfc_probe()
383 		sfc->version = SFC_VER_6;  in rockchip_sfc_probe()
385 	ret = rockchip_sfc_init(sfc);  in rockchip_sfc_probe()
389 	sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);  in rockchip_sfc_probe()
390 	sfc->max_freq = SFC_MAX_SPEED;  in rockchip_sfc_probe()
391 	sfc->dev = bus;  in rockchip_sfc_probe()
397 	clk_disable(&sfc->clk);  in rockchip_sfc_probe()
398 	clk_disable(&sfc->hclk);  in rockchip_sfc_probe()
404 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)  in rockchip_sfc_wait_txfifo_ready()  argument
409 	ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,  in rockchip_sfc_wait_txfifo_ready()
413 		dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");  in rockchip_sfc_wait_txfifo_ready()
421 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)  in rockchip_sfc_wait_rxfifo_ready()  argument
426 	ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,  in rockchip_sfc_wait_rxfifo_ready()
430 		dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");  in rockchip_sfc_wait_rxfifo_ready()
453 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)  in rockchip_sfc_wait_for_dma_finished()  argument
459 	while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {  in rockchip_sfc_wait_for_dma_finished()
462 			rockchip_sfc_reset(sfc);  in rockchip_sfc_wait_for_dma_finished()
470 	writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);  in rockchip_sfc_wait_for_dma_finished()
475 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,  in rockchip_sfc_xfer_setup()  argument
495 			writel(op->addr.nbytes * 8 - 1, sfc->regbase + plat->cs * SFC_CS1_REG_OFFSET + SFC_ABIT);  in rockchip_sfc_xfer_setup()
512 	if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */  in rockchip_sfc_xfer_setup()
513 		writel(len, sfc->regbase + SFC_LEN_EXT);  in rockchip_sfc_xfer_setup()
529 	dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",  in rockchip_sfc_xfer_setup()
532 	dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x cs=%x\n",  in rockchip_sfc_xfer_setup()
535 	writel(ctrl, sfc->regbase + plat->cs * SFC_CS1_REG_OFFSET + SFC_CTRL);  in rockchip_sfc_xfer_setup()
536 	writel(cmd, sfc->regbase + SFC_CMD);  in rockchip_sfc_xfer_setup()
538 		writel(op->addr.val, sfc->regbase + SFC_ADDR);  in rockchip_sfc_xfer_setup()
543 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)  in rockchip_sfc_write_fifo()  argument
553 		tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);  in rockchip_sfc_write_fifo()
557 		writesl(sfc->regbase + SFC_DATA, buf, write_words);  in rockchip_sfc_write_fifo()
564 		tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);  in rockchip_sfc_write_fifo()
568 		writel(tmp, sfc->regbase + SFC_DATA);  in rockchip_sfc_write_fifo()
574 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)  in rockchip_sfc_read_fifo()  argument
585 		rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);  in rockchip_sfc_read_fifo()
589 		readsl(sfc->regbase + SFC_DATA, buf, read_words);  in rockchip_sfc_read_fifo()
596 		rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);  in rockchip_sfc_read_fifo()
599 		tmp = readl(sfc->regbase + SFC_DATA);  in rockchip_sfc_read_fifo()
606 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)  in rockchip_sfc_fifo_transfer_dma()  argument
608 	writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);  in rockchip_sfc_fifo_transfer_dma()
609 	writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);  in rockchip_sfc_fifo_transfer_dma()
610 	writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);  in rockchip_sfc_fifo_transfer_dma()
615 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,  in rockchip_sfc_xfer_data_poll()  argument
618 	dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);  in rockchip_sfc_xfer_data_poll()
621 		return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);  in rockchip_sfc_xfer_data_poll()
623 		return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);  in rockchip_sfc_xfer_data_poll()
626 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,  in rockchip_sfc_xfer_data_dma()  argument
634 	dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);  in rockchip_sfc_xfer_data_dma()
648 	ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);  in rockchip_sfc_xfer_data_dma()
649 	rockchip_sfc_wait_for_dma_finished(sfc, len * 10);  in rockchip_sfc_xfer_data_dma()
655 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc,  in rockchip_sfc_xfer_data_dma_async()  argument
668 	dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf);  in rockchip_sfc_xfer_data_dma_async()
670 	rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len);  in rockchip_sfc_xfer_data_dma_async()
671 	sfc->last_async_size = len;  in rockchip_sfc_xfer_data_dma_async()
676 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)  in rockchip_sfc_xfer_done()  argument
681 	ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,  in rockchip_sfc_xfer_done()
685 		dev_err(sfc->dev, "wait sfc idle timeout\n");  in rockchip_sfc_xfer_done()
686 		rockchip_sfc_reset(sfc);  in rockchip_sfc_xfer_done()
694 static int rockchip_spi_set_cs(struct rockchip_sfc *sfc, struct spi_slave *mem, bool enable)  in rockchip_spi_set_cs()  argument
700 	if (!dm_gpio_is_valid(&sfc->cs_gpios[cs]))  in rockchip_spi_set_cs()
704 	dm_gpio_set_value(&sfc->cs_gpios[cs], enable);  in rockchip_spi_set_cs()
710 static int rockchip_sfc_exec_op_bypass(struct rockchip_sfc *sfc,  in rockchip_sfc_exec_op_bypass()  argument
714 	u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);  in rockchip_sfc_exec_op_bypass()
718 	rockchip_spi_set_cs(sfc, mem, true);  in rockchip_sfc_exec_op_bypass()
719 	rockchip_sfc_xfer_setup(sfc, mem, op, len);  in rockchip_sfc_exec_op_bypass()
720 	ret = rockchip_sfc_xfer_data_poll(sfc, op, len);  in rockchip_sfc_exec_op_bypass()
722 		dev_err(sfc->dev, "xfer data failed ret %d\n", ret);  in rockchip_sfc_exec_op_bypass()
727 	ret = rockchip_sfc_xfer_done(sfc, 100000);  in rockchip_sfc_exec_op_bypass()
728 	rockchip_spi_set_cs(sfc, mem, false);  in rockchip_sfc_exec_op_bypass()
733 static void rockchip_sfc_delay_lines_tuning(struct rockchip_sfc *sfc, struct spi_slave *mem)  in rockchip_sfc_delay_lines_tuning()  argument
741 	u16 cell_max = (u16)rockchip_sfc_get_max_dll_cells(sfc);  in rockchip_sfc_delay_lines_tuning()
747 	rockchip_sfc_clk_set_rate(sfc, SFC_DLL_THRESHOLD_RATE);  in rockchip_sfc_delay_lines_tuning()
749 	rockchip_sfc_exec_op_bypass(sfc, mem, &op);  in rockchip_sfc_delay_lines_tuning()
752 		dev_dbg(sfc->dev, "no dev, dll by pass\n");  in rockchip_sfc_delay_lines_tuning()
753 		rockchip_sfc_clk_set_rate(sfc, sfc->speed[cs]);  in rockchip_sfc_delay_lines_tuning()
754 		sfc->speed[cs] = SFC_DLL_THRESHOLD_RATE;  in rockchip_sfc_delay_lines_tuning()
759 	rockchip_sfc_clk_set_rate(sfc, sfc->speed[cs]);  in rockchip_sfc_delay_lines_tuning()
764 		rockchip_sfc_set_delay_lines(sfc, right, cs);  in rockchip_sfc_delay_lines_tuning()
765 		rockchip_sfc_exec_op_bypass(sfc, mem, &op);  in rockchip_sfc_delay_lines_tuning()
766 		dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n",  in rockchip_sfc_delay_lines_tuning()
790 			sfc->dll_cells[cs] = left + (right - left) * 2 / 5;  in rockchip_sfc_delay_lines_tuning()
792 			sfc->dll_cells[cs] = left + (right - left) / 2;  in rockchip_sfc_delay_lines_tuning()
794 		sfc->dll_cells[cs] = 0;  in rockchip_sfc_delay_lines_tuning()
797 	if (sfc->dll_cells[cs]) {  in rockchip_sfc_delay_lines_tuning()
798 		dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n",  in rockchip_sfc_delay_lines_tuning()
799 			left, right, sfc->dll_cells[cs], sfc->speed[cs],  in rockchip_sfc_delay_lines_tuning()
800 			rockchip_sfc_get_max_dll_cells(sfc), rockchip_sfc_get_version(sfc));  in rockchip_sfc_delay_lines_tuning()
801 		rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells[cs], cs);  in rockchip_sfc_delay_lines_tuning()
803 		sfc->speed[1] = sfc->cur_speed;  in rockchip_sfc_delay_lines_tuning()
804 		sfc->dll_cells[1] = sfc->dll_cells[0];  in rockchip_sfc_delay_lines_tuning()
805 		rockchip_sfc_set_delay_lines(sfc, (u16)sfc->dll_cells[1], 1);  in rockchip_sfc_delay_lines_tuning()
808 		dev_err(sfc->dev, "%d %d dll training failed in %dMHz, reduce the speed\n",  in rockchip_sfc_delay_lines_tuning()
809 			left, right, sfc->speed[cs]);  in rockchip_sfc_delay_lines_tuning()
810 		rockchip_sfc_set_delay_lines(sfc, 0, cs);  in rockchip_sfc_delay_lines_tuning()
811 		rockchip_sfc_clk_set_rate(sfc, SFC_DLL_THRESHOLD_RATE);  in rockchip_sfc_delay_lines_tuning()
812 		sfc->cur_speed = SFC_DLL_THRESHOLD_RATE;  in rockchip_sfc_delay_lines_tuning()
813 		sfc->cur_real_speed = rockchip_sfc_clk_get_rate(sfc);  in rockchip_sfc_delay_lines_tuning()
814 		sfc->speed[cs] = SFC_DLL_THRESHOLD_RATE;  in rockchip_sfc_delay_lines_tuning()
823 	struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent);  in rockchip_sfc_exec_op()  local
825 	u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);  in rockchip_sfc_exec_op()
832 	if (rockchip_sfc_get_version(sfc) >= SFC_VER_4 &&  in rockchip_sfc_exec_op()
833 	    sfc->cur_speed != sfc->speed[plat->cs]) {  in rockchip_sfc_exec_op()
834 		sfc->speed[plat->cs] = sfc->cur_speed;  in rockchip_sfc_exec_op()
836 		if (sfc->cur_real_speed > SFC_DLL_THRESHOLD_RATE)  in rockchip_sfc_exec_op()
837 			rockchip_sfc_delay_lines_tuning(sfc, mem);  in rockchip_sfc_exec_op()
840 			rockchip_sfc_set_delay_lines(sfc, 0, plat->cs);  in rockchip_sfc_exec_op()
844 	if (sfc->last_async_size) {  in rockchip_sfc_exec_op()
845 		rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size);  in rockchip_sfc_exec_op()
846 		sfc->last_async_size = 0;  in rockchip_sfc_exec_op()
849 	rockchip_spi_set_cs(sfc, mem, true);  in rockchip_sfc_exec_op()
850 	rockchip_sfc_xfer_setup(sfc, mem, op, len);  in rockchip_sfc_exec_op()
852 		if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) {  in rockchip_sfc_exec_op()
854 				return rockchip_sfc_xfer_data_dma_async(sfc, op, len);  in rockchip_sfc_exec_op()
855 			ret = rockchip_sfc_xfer_data_dma(sfc, op, len);  in rockchip_sfc_exec_op()
857 			ret = rockchip_sfc_xfer_data_poll(sfc, op, len);  in rockchip_sfc_exec_op()
861 			dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);  in rockchip_sfc_exec_op()
867 	ret = rockchip_sfc_xfer_done(sfc, 100000);  in rockchip_sfc_exec_op()
868 	rockchip_spi_set_cs(sfc, mem, false);  in rockchip_sfc_exec_op()
875 	struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent);  in rockchip_sfc_adjust_op_size()  local
877 	op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);  in rockchip_sfc_adjust_op_size()
884 	struct rockchip_sfc *sfc = dev_get_platdata(bus);  in rockchip_sfc_set_speed()  local
886 	if (speed > sfc->max_freq)  in rockchip_sfc_set_speed()
887 		speed = sfc->max_freq;  in rockchip_sfc_set_speed()
889 	if (speed == sfc->cur_speed)  in rockchip_sfc_set_speed()
893 	int ret = rockchip_sfc_clk_set_rate(sfc, speed);  in rockchip_sfc_set_speed()
896 		dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",  in rockchip_sfc_set_speed()
900 	sfc->cur_speed = speed;  in rockchip_sfc_set_speed()
901 	sfc->cur_real_speed = rockchip_sfc_clk_get_rate(sfc);  in rockchip_sfc_set_speed()
903 	dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%dHz\n",  in rockchip_sfc_set_speed()
904 		sfc->cur_speed, sfc->cur_real_speed);  in rockchip_sfc_set_speed()
906 	dev_dbg(sfc->dev, "sfc failed, CLK not support\n");  in rockchip_sfc_set_speed()