221 	dev_dbg(sfc->dev, "reset\n");  in rockchip_sfc_reset()
374 		dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);  in rockchip_sfc_probe()
378 		dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);  in rockchip_sfc_probe()
413 		dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");  in rockchip_sfc_wait_txfifo_ready()
430 		dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");  in rockchip_sfc_wait_rxfifo_ready()
529 	dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",  in rockchip_sfc_xfer_setup()
532 	dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x cs=%x\n",  in rockchip_sfc_xfer_setup()
618 	dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);  in rockchip_sfc_xfer_data_poll()
634 	dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);  in rockchip_sfc_xfer_data_dma()
668 	dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf);  in rockchip_sfc_xfer_data_dma_async()
752 		dev_dbg(sfc->dev, "no dev, dll by pass\n");  in rockchip_sfc_delay_lines_tuning()
766 		dev_dbg(sfc->dev, "dll read flash id:%x %x %x\n",  in rockchip_sfc_delay_lines_tuning()
798 		dev_dbg(sfc->dev, "%d %d %d dll training success in %dMHz max_cells=%u sfc_ver=%d\n",  in rockchip_sfc_delay_lines_tuning()
903 	dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%dHz\n",  in rockchip_sfc_set_speed()
906 	dev_dbg(sfc->dev, "sfc failed, CLK not support\n");  in rockchip_sfc_set_speed()