Lines Matching refs:CQSPI_REG_CONFIG
52 #define CQSPI_REG_CONFIG 0x00 macro
162 ((readl(base + CQSPI_REG_CONFIG) >> \
189 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
191 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
197 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
199 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
260 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
278 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
288 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
296 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
311 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
330 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
777 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()
781 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()