34 #ifdef dev_err
35 #undef dev_err
36 #define dev_err(dev, fmt, ...) \  macro
46 #define dev_info dev_err
50 #define dev_dbg dev_err
225 		dev_err(rk_pcie->dev, "Read APB address failed\n");  in __rk_pcie_read_apb()
237 		dev_err(rk_pcie->dev, "Write APB address failed\n");  in __rk_pcie_write_apb()
410 		dev_err(pci->dev, "cap_lanes %u: invalid value\n", cap_lanes);  in rk_pcie_configure()
473 	dev_err(pci->dev, "outbound iATU is not being enabled\n");  in rk_pcie_prog_outbound_atu_unroll()
610 	dev_err(rk_pcie->dev, "ltssm = 0x%x\n",  in rk_pcie_debug_dump()
613 		dev_err(rk_pcie->dev, "fifo_status = 0x%x\n",  in rk_pcie_debug_dump()
696 	dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq);  in rk_pcie_link_up()
719 			dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n",  in rockchip_pcie_init_port()
729 			dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret);  in rockchip_pcie_init_port()
734 		dev_err(dev, "failed to init phy (ret=%d)\n", ret);  in rockchip_pcie_init_port()
740 		dev_err(dev, "failed to power on phy (ret=%d)\n", ret);  in rockchip_pcie_init_port()
746 		dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);  in rockchip_pcie_init_port()
752 		dev_err(dev, "failed to enable clks (ret=%d)\n", ret);  in rockchip_pcie_init_port()
818 		dev_err(dev, "failed to find reset-gpios property\n");  in rockchip_pcie_parse_dt()
824 		dev_err(dev, "Can't get reset: %d\n", ret);  in rockchip_pcie_parse_dt()
830 		dev_err(dev, "Can't get clock: %d\n", ret);  in rockchip_pcie_parse_dt()
837 		dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);  in rockchip_pcie_parse_dt()
843 		dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);  in rockchip_pcie_parse_dt()
905 			dev_err(dev, "don't support prefetchable memory, please fix your dtb.\n");  in rockchip_pcie_probe()
907 			dev_err(dev, "invalid flags type\n");  in rockchip_pcie_probe()