62 	void		*dbi_base;  member
261 	header = readl(rk_pcie->dbi_base + pos);  in rk_pci_find_ext_capability()
278 		header = readl(rk_pcie->dbi_base + pos);  in rk_pci_find_ext_capability()
288 	return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) &  in rk_pcie_get_link_speed()
294 	return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) &  in rk_pcie_get_link_width()
302 	void __iomem *base = rk_pcie->dbi_base;  in rk_pcie_writel_ob_unroll()
310 	void __iomem *base = rk_pcie->dbi_base;  in rk_pcie_readl_ob_unroll()
319 	val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF);  in rk_pcie_dbi_write_enable()
325 	writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF);  in rk_pcie_dbi_write_enable()
336 	       rk_pcie->dbi_base + PCI_BASE_ADDRESS_0);  in rk_pcie_setup_host()
337 	writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1);  in rk_pcie_setup_host()
340 	val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE);  in rk_pcie_setup_host()
343 	writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE);  in rk_pcie_setup_host()
346 	val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS);  in rk_pcie_setup_host()
349 	writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS);  in rk_pcie_setup_host()
351 	val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS);  in rk_pcie_setup_host()
354 	val = readl(rk_pcie->dbi_base + PCI_COMMAND);  in rk_pcie_setup_host()
358 	writel(val, rk_pcie->dbi_base + PCI_COMMAND);  in rk_pcie_setup_host()
361 	writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE);  in rk_pcie_setup_host()
364 	val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in rk_pcie_setup_host()
366 	writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in rk_pcie_setup_host()
369 	writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);  in rk_pcie_setup_host()
370 	writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);  in rk_pcie_setup_host()
381 	val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);  in rk_pcie_configure()
384 	writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);  in rk_pcie_configure()
386 	val = readl(pci->dbi_base + PCIE_LINK_CTL_2);  in rk_pcie_configure()
389 	writel(val, pci->dbi_base + PCIE_LINK_CTL_2);  in rk_pcie_configure()
391 	val = readl(pci->dbi_base + PCIE_PORT_LINK_CONTROL);  in rk_pcie_configure()
413 	writel(val, pci->dbi_base + PCIE_PORT_LINK_CONTROL);  in rk_pcie_configure()
416 	val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in rk_pcie_configure()
432 	writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in rk_pcie_configure()
495 		va_address = (uintptr_t)pcie->dbi_base;  in set_cfg_address()
806 	priv->dbi_base = (void *)(res.start);  in rockchip_pcie_parse_dt()
807 	dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base);  in rockchip_pcie_parse_dt()
974 		writel(0x1c, priv->dbi_base + priv->rasdes_off + 8);  in rockchip_pcie_probe()
975 		writel(0x3, priv->dbi_base + priv->rasdes_off + 8);  in rockchip_pcie_probe()
986 	writel(v, priv->dbi_base + cap_base + 8); \
987 	printf(ss "0x%x\n", readl(priv->dbi_base + cap_base + 0xc)); \