1173 	val = readl(&eqos->dma_regs->mode);  in eqos_init()
1175 	writel(val, &eqos->dma_regs->mode);  in eqos_init()
1177 		if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))  in eqos_init()
1414 	setbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_enable()
1418 	clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_enable()
1424 	setbits_le32(&eqos->dma_regs->ch0_control,  in eqos_enable()
1436 	clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_enable()
1441 	clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_enable()
1450 	writel(val, &eqos->dma_regs->sysbus_mode);  in eqos_enable()
1467 	writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);  in eqos_enable()
1468 	writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);  in eqos_enable()
1470 	       &eqos->dma_regs->ch0_txdesc_ring_length);  in eqos_enable()
1472 	writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);  in eqos_enable()
1473 	writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);  in eqos_enable()
1475 	       &eqos->dma_regs->ch0_rxdesc_ring_length);  in eqos_enable()
1478 	setbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_enable()
1480 	setbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_enable()
1493 	writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);  in eqos_enable()
1524 	clrbits_le32(&eqos->dma_regs->ch0_tx_control,  in eqos_stop()
1553 	clrbits_le32(&eqos->dma_regs->ch0_rx_control,  in eqos_stop()
1593 		&eqos->dma_regs->ch0_txdesc_tail_pointer);  in eqos_send()
1667 	writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);  in eqos_free_pkt()
2032 	eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);  in eqos_probe()