drivers/mmc/sdhci.c

23 static void sdhci_reset(struct sdhci_host *host, u8 mask)  in sdhci_reset()  argument
29 	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);  in sdhci_reset()
30 	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {  in sdhci_reset()
41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)  in sdhci_cmd_done()  argument
47 			cmd->response[i] = sdhci_readl(host,  in sdhci_cmd_done()
50 				cmd->response[i] |= sdhci_readb(host,  in sdhci_cmd_done()
54 		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);  in sdhci_cmd_done()
58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)  in sdhci_transfer_pio()  argument
65 			*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);  in sdhci_transfer_pio()
67 			sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);  in sdhci_transfer_pio()
71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,  in sdhci_transfer_data()  argument
78 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);  in sdhci_transfer_data()
80 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);  in sdhci_transfer_data()
87 		stat = sdhci_readl(host, SDHCI_INT_STATUS);  in sdhci_transfer_data()
94 			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))  in sdhci_transfer_data()
96 			sdhci_writel(host, rdy, SDHCI_INT_STATUS);  in sdhci_transfer_data()
97 			sdhci_transfer_pio(host, data);  in sdhci_transfer_data()
110 			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);  in sdhci_transfer_data()
113 			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);  in sdhci_transfer_data()
148 	struct sdhci_host *host = mmc->priv;  local
170 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
177 				sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
188 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
218 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
232 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
251 		sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
254 		sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
257 		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
258 		sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
260 		sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
263 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
270 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
273 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
278 			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
289 		sdhci_cmd_done(host, cmd);
290 		sdhci_writel(host, mask, SDHCI_INT_STATUS);
295 		ret = sdhci_transfer_data(host, data, start_addr);
297 	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
300 	stat = sdhci_readl(host, SDHCI_INT_STATUS);
301 	sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
303 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
309 	sdhci_reset(host, SDHCI_RESET_CMD);
310 	sdhci_reset(host, SDHCI_RESET_DATA);
317 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)  argument
322 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
326 	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
337 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
340 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock)  argument
346 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
357 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
361 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
366 		if (host->clk_mul) {
368 				if ((host->max_clk / div) <= clock)
380 			if (host->max_clk <= clock) {
386 					if ((host->max_clk / div) <= clock)
395 			if ((host->max_clk / div) <= clock)
400 	if (host->ops && host->ops->set_clock_ext)
401 		host->ops->set_clock_ext(host, div);
407 	sdhci_enable_clk(host, clk);
409 	host->clock = clock;
413 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)  argument
434 		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
440 	sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
443 static void sdhci_set_uhs_signaling(struct sdhci_host *host)  argument
446 	u32 timing = host->mmc->timing;
448 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
474 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
485 	struct sdhci_host *host = mmc->priv;  local
489 	present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
503 	struct sdhci_host *host = mmc->priv;  local
505 	if (host->ops && host->ops->set_control_reg)
506 		host->ops->set_control_reg(host);
508 	if (mmc->clock != host->clock) {
509 		if (host->ops && host->ops->set_clock)
510 			host->ops->set_clock(host, mmc->clock);
512 			sdhci_set_clock(host, mmc->clock);
516 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
519 		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
520 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
523 		if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
524 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
533 	    !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
538 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
543 		sdhci_set_power(host, MMC_VDD_165_195_SHIFT);
545 	sdhci_set_uhs_signaling(host);
548 	if (host->ops && host->ops->set_ios_post)
549 		host->ops->set_ios_post(host);
556 	struct sdhci_host *host = mmc->priv;  local
558 	sdhci_reset(host, SDHCI_RESET_ALL);
560 	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
569 	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
571 	if (host->ops && host->ops->get_cd)
572 		host->ops->get_cd(host);
575 	sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
578 	sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
583 static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode)  argument
596 	    host->mmc->bus_width == MMC_BUS_WIDTH_8BIT)
597 		sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
599 		sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
607 	sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
610 	return sdhci_send_command(host->mmc->dev, &cmd, NULL);
612 	return sdhci_send_command(host->mmc, &cmd, NULL);
617 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)  argument
629 		ret = sdhci_send_tuning(host, opcode);
634 		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
654 	struct sdhci_host *host = mmc->priv;  local
678 	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
680 	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
682 	return __sdhci_execute_tuning(host, opcode);
696 	struct sdhci_host *host = mmc->priv;  local
698 	if (host->ops && host->ops->set_enhanced_strobe)
699 		return host->ops->set_enhanced_strobe(host);
721 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,  argument
726 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
735 	if (host->quirks & SDHCI_QUIRK_REG32_RW)
736 		host->version =
737 			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
739 		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
741 	cfg->name = host->name;
747 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
748 		caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
749 		host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
753 	if (host->max_clk == 0) {
754 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
755 			host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
758 			host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
760 		host->max_clk *= 1000000;
761 		if (host->clk_mul)
762 			host->max_clk *= host->clk_mul;
764 	if (host->max_clk == 0) {
769 	if (f_max && (f_max < host->max_clk))
772 		cfg->f_max = host->max_clk;
776 		if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
789 	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
790 		cfg->voltages |= host->voltages;
795 	if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
800 	if (host->host_caps)
801 		cfg->host_caps |= host->host_caps;
814 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)  argument
818 	ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
822 	host->mmc = mmc_create(&host->cfg, host);
823 	if (host->mmc == NULL) {