55 			u32 bit, unsigned char flag)  in gpio_bit_op()  argument
59 	offset = REG_PLUS4(offset, bit);  in gpio_bit_op()
60 	bit = BIT_SUB16(bit);  in gpio_bit_op()
62 	val = flag ? WMSK_SETBIT(bit) : WMSK_CLRBIT(bit);  in gpio_bit_op()
66 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit)  in gpio_bit_rd()  argument
68 	offset = REG_PLUS4(offset, bit);  in gpio_bit_rd()
69 	bit = BIT_SUB16(bit);  in gpio_bit_rd()
71 	return readl(regbase + offset) & bit ? 1 : 0;  in gpio_bit_rd()
74 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit)  in gpio_irq_unmask()  argument
76 	gpio_bit_op(regbase, GPIO_INTEN, bit, 1);  in gpio_irq_unmask()
79 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit)  in gpio_irq_mask()  argument
81 	gpio_bit_op(regbase, GPIO_INTEN, bit, 0);  in gpio_irq_mask()
84 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit)  in gpio_irq_ack()  argument
86 	gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1);  in gpio_irq_ack()
133 			       unsigned int bit,  in gpio_set_intr_type()  argument
138 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);  in gpio_set_intr_type()
139 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);  in gpio_set_intr_type()
142 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0);  in gpio_set_intr_type()
143 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);  in gpio_set_intr_type()
146 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);  in gpio_set_intr_type()
147 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0);  in gpio_set_intr_type()
150 		gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1);  in gpio_set_intr_type()
151 		gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1);  in gpio_set_intr_type()
157 			      unsigned int bit)  in gpio_get_intr_type()  argument
162 	polarity = gpio_bit_rd(regbase, GPIO_INT_POLARITY, bit);  in gpio_get_intr_type()
163 	level = gpio_bit_rd(regbase, GPIO_INTTYPE_LEVEL, bit);  in gpio_get_intr_type()