Lines Matching refs:src_clk_div
239 int src_clk_div; in rv1126_i2c_set_pmuclk() local
241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
242 assert(src_clk_div - 1 <= 127); in rv1126_i2c_set_pmuclk()
247 (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); in rv1126_i2c_set_pmuclk()
251 (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT); in rv1126_i2c_set_pmuclk()
292 int src_clk_div; in rv1126_pwm_set_pmuclk() local
303 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
304 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_pmuclk()
307 (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); in rv1126_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
322 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_pmuclk()
325 (src_clk_div - 1) << CLK_PWM1_DIV_SHIFT); in rv1126_pwm_set_pmuclk()
353 int src_clk_div; in rv1126_spi_set_pmuclk() local
355 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_pmuclk()
356 assert(src_clk_div - 1 <= 127); in rv1126_spi_set_pmuclk()
361 (src_clk_div - 1) << CLK_SPI0_DIV_SHIFT); in rv1126_spi_set_pmuclk()
381 int src_clk_div; in rv1126_pdpmu_set_pmuclk() local
383 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdpmu_set_pmuclk()
384 assert(src_clk_div - 1 <= 31); in rv1126_pdpmu_set_pmuclk()
388 (src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT); in rv1126_pdpmu_set_pmuclk()
610 int src_clk_div; in rv1126_pdcore_set_clk() local
611 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdcore_set_clk()
612 assert(src_clk_div - 1 <= 31); in rv1126_pdcore_set_clk()
615 (src_clk_div - 1) << CORE_HCLK_DIV_SHIFT); in rv1126_pdcore_set_clk()
671 int src_clk_div, clk_sel; in rv1126_pdbus_set_clk() local
676 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
679 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_pdbus_set_clk()
682 assert(src_clk_div - 1 <= 31); in rv1126_pdbus_set_clk()
686 (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT); in rv1126_pdbus_set_clk()
689 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
690 assert(src_clk_div - 1 <= 31); in rv1126_pdbus_set_clk()
694 (src_clk_div - 1) << HCLK_PDBUS_DIV_SHIFT); in rv1126_pdbus_set_clk()
698 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
699 assert(src_clk_div - 1 <= 31); in rv1126_pdbus_set_clk()
703 (src_clk_div - 1) << PCLK_PDBUS_DIV_SHIFT); in rv1126_pdbus_set_clk()
741 int src_clk_div; in rv1126_pdphp_set_clk() local
743 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdphp_set_clk()
744 assert(src_clk_div - 1 <= 31); in rv1126_pdphp_set_clk()
751 (src_clk_div - 1) << ACLK_PDPHP_DIV_SHIFT); in rv1126_pdphp_set_clk()
756 (src_clk_div - 1) << HCLK_PDPHP_DIV_SHIFT); in rv1126_pdphp_set_clk()
780 int src_clk_div; in rv1126_pdaudio_set_clk() local
782 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdaudio_set_clk()
783 assert(src_clk_div - 1 <= 31); in rv1126_pdaudio_set_clk()
786 (src_clk_div - 1) << HCLK_PDAUDIO_DIV_SHIFT); in rv1126_pdaudio_set_clk()
824 int src_clk_div; in rv1126_i2c_set_clk() local
826 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_clk()
827 assert(src_clk_div - 1 <= 127); in rv1126_i2c_set_clk()
832 (src_clk_div - 1) << CLK_I2C1_DIV_SHIFT); in rv1126_i2c_set_clk()
836 (src_clk_div - 1) << CLK_I2C3_DIV_SHIFT); in rv1126_i2c_set_clk()
840 (src_clk_div - 1) << CLK_I2C4_DIV_SHIFT); in rv1126_i2c_set_clk()
844 (src_clk_div - 1) << CLK_I2C5_DIV_SHIFT); in rv1126_i2c_set_clk()
867 int src_clk_div; in rv1126_spi_set_clk() local
869 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_clk()
870 assert(src_clk_div - 1 <= 127); in rv1126_spi_set_clk()
875 (src_clk_div - 1) << CLK_SPI1_DIV_SHIFT); in rv1126_spi_set_clk()
897 int src_clk_div; in rv1126_pwm_set_clk() local
904 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_clk()
905 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_clk()
907 (src_clk_div - 1) << CLK_PWM2_DIV_SHIFT); in rv1126_pwm_set_clk()
929 int src_clk_div; in rv1126_saradc_set_clk() local
931 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rv1126_saradc_set_clk()
932 assert(src_clk_div - 1 <= 2047); in rv1126_saradc_set_clk()
934 (src_clk_div - 1) << CLK_SARADC_DIV_SHIFT); in rv1126_saradc_set_clk()
989 int src_clk_div; in rv1126_crypto_set_clk() local
991 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_crypto_set_clk()
992 assert(src_clk_div - 1 <= 31); in rv1126_crypto_set_clk()
1001 (src_clk_div - 1) << CLK_CRYPTO_CORE_DIV_SHIFT); in rv1126_crypto_set_clk()
1009 (src_clk_div - 1) << CLK_CRYPTO_PKA_DIV_SHIFT); in rv1126_crypto_set_clk()
1015 (src_clk_div - 1) << ACLK_CRYPTO_DIV_SHIFT); in rv1126_crypto_set_clk()
1064 int src_clk_div; in rv1126_mmc_set_clk() local
1086 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate); in rv1126_mmc_set_clk()
1088 if (src_clk_div > 127) { in rv1126_mmc_set_clk()
1090 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate); in rv1126_mmc_set_clk()
1094 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rv1126_mmc_set_clk()
1099 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rv1126_mmc_set_clk()
1126 int src_clk_div; in rv1126_sfc_set_clk() local
1128 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_sfc_set_clk()
1132 (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); in rv1126_sfc_set_clk()
1158 int src_clk_div; in rv1126_nand_set_clk() local
1160 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_nand_set_clk()
1164 (src_clk_div - 1) << CLK_NANDC_DIV_SHIFT); in rv1126_nand_set_clk()
1190 int src_clk_div; in rv1126_aclk_vop_set_clk() local
1192 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_aclk_vop_set_clk()
1193 assert(src_clk_div - 1 <= 31); in rv1126_aclk_vop_set_clk()
1197 (src_clk_div - 1) << ACLK_PDVO_DIV_SHIFT); in rv1126_aclk_vop_set_clk()
1287 int src_clk_div; in rv1126_scr1_set_clk() local
1289 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_scr1_set_clk()
1290 assert(src_clk_div - 1 <= 31); in rv1126_scr1_set_clk()
1294 (src_clk_div - 1) << CLK_SCR1_DIV_SHIFT); in rv1126_scr1_set_clk()
1320 int src_clk_div; in rv1126_gmac_src_set_clk() local
1322 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_gmac_src_set_clk()
1323 assert(src_clk_div - 1 <= 31); in rv1126_gmac_src_set_clk()
1327 (src_clk_div - 1) << CLK_GMAC_SRC_DIV_SHIFT); in rv1126_gmac_src_set_clk()
1353 int src_clk_div; in rv1126_gmac_out_set_clk() local
1355 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_gmac_out_set_clk()
1356 assert(src_clk_div - 1 <= 31); in rv1126_gmac_out_set_clk()
1360 (src_clk_div - 1) << CLK_GMAC_OUT_DIV_SHIFT); in rv1126_gmac_out_set_clk()
1432 int src_clk_div; in rv1126_clk_mipicsi_out_set_clk() local
1438 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, 297000000); in rv1126_clk_mipicsi_out_set_clk()
1440 (src_clk_div - 1) << MIPICSI_OUT_DIV_SHIFT); in rv1126_clk_mipicsi_out_set_clk()
1445 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_clk_mipicsi_out_set_clk()
1446 assert(src_clk_div - 1 <= 31); in rv1126_clk_mipicsi_out_set_clk()
1448 (src_clk_div - 1) << MIPICSI_OUT_DIV_SHIFT); in rv1126_clk_mipicsi_out_set_clk()
1495 u32 parent, sel, src_clk_div, con_id; in rv1126_clk_pdvi_ispp_set_clk() local
1522 src_clk_div = DIV_ROUND_UP(parent, rate); in rv1126_clk_pdvi_ispp_set_clk()
1523 assert(src_clk_div - 1 <= 31); in rv1126_clk_pdvi_ispp_set_clk()
1527 (src_clk_div - 1) << ACLK_PDVI_DIV_SHIFT); in rv1126_clk_pdvi_ispp_set_clk()
1555 u32 parent, sel, src_clk_div; in rv1126_clk_isp_set_clk() local
1568 src_clk_div = DIV_ROUND_UP(parent, rate); in rv1126_clk_isp_set_clk()
1569 assert(src_clk_div - 1 <= 31); in rv1126_clk_isp_set_clk()
1573 (src_clk_div - 1) << CLK_ISP_DIV_SHIFT); in rv1126_clk_isp_set_clk()
1600 u32 src_clk_div; in rv1126_dclk_decom_set_clk() local
1602 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_dclk_decom_set_clk()
1603 assert(src_clk_div - 1 <= 127); in rv1126_dclk_decom_set_clk()
1607 (src_clk_div - 1) << DCLK_DECOM_DIV_SHIFT); in rv1126_dclk_decom_set_clk()