Lines Matching refs:DIV_TO_RATE
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro
165 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
186 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
197 return DIV_TO_RATE(OSC_HZ, div); in rv1108_saradc_get_clk()
222 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_aclk_vio1_get_clk()
248 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_aclk_vio0_get_clk()
283 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_dclk_vop_get_clk()
312 return DIV_TO_RATE(parent_rate, div); in rv1108_aclk_bus_get_clk()
340 return DIV_TO_RATE(parent_rate, div); in rv1108_aclk_peri_get_clk()
352 return DIV_TO_RATE(parent_rate, div); in rv1108_hclk_peri_get_clk()
364 return DIV_TO_RATE(parent_rate, div); in rv1108_pclk_peri_get_clk()
443 return DIV_TO_RATE(GPLL_HZ, div); in rv1108_i2c_get_clk()
494 return DIV_TO_RATE(rkclk_pll_get_rate(cru, CLK_GENERAL), div); in rv1108_spi_get_clk()
521 mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2; in rv1108_mmc_get_clk()
523 mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2; in rv1108_mmc_get_clk()
554 return DIV_TO_RATE(pll_rate, div); in rv1108_mmc_set_clk()