Lines Matching refs:src_clk_div
332 int src_clk, src_clk_div; in rk3588_top_set_clk() local
338 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
343 assert(src_clk_div - 1 <= 31); in rk3588_top_set_clk()
349 (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT); in rk3588_top_set_clk()
352 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
353 assert(src_clk_div - 1 <= 31); in rk3588_top_set_clk()
359 (src_clk_div - 1) << ACLK_LOW_TOP_ROOT_DIV_SHIFT); in rk3588_top_set_clk()
689 int src_clk_div; in rk3588_adc_set_clk() local
694 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
695 assert(src_clk_div - 1 <= 255); in rk3588_adc_set_clk()
701 (src_clk_div - 1) << in rk3588_adc_set_clk()
704 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
705 assert(src_clk_div - 1 <= 255); in rk3588_adc_set_clk()
711 (src_clk_div - 1) << in rk3588_adc_set_clk()
717 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
718 assert(src_clk_div - 1 <= 255); in rk3588_adc_set_clk()
724 (src_clk_div - 1) << in rk3588_adc_set_clk()
727 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
728 assert(src_clk_div - 1 <= 7); in rk3588_adc_set_clk()
734 (src_clk_div - 1) << in rk3588_adc_set_clk()