1325 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3588_uart_get_rate()  local
1360 	src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;  in rk3588_uart_get_rate()
1369 	if (src == CLK_UART_SEL_SRC) {  in rk3588_uart_get_rate()
1371 	} else if (src == CLK_UART_SEL_FRAC) {  in rk3588_uart_get_rate()
1462 	u32 con, div, src;  in rk3588_pciephy_get_rate()  local
1467 		src = (con & CLK_PCIE_PHY0_REF_SEL_MASK) >> CLK_PCIE_PHY0_REF_SEL_SHIFT;  in rk3588_pciephy_get_rate()
1473 		src = (con & CLK_PCIE_PHY1_REF_SEL_MASK) >> CLK_PCIE_PHY1_REF_SEL_SHIFT;  in rk3588_pciephy_get_rate()
1479 		src = (con & CLK_PCIE_PHY2_REF_SEL_MASK) >> CLK_PCIE_PHY2_REF_SEL_SHIFT;  in rk3588_pciephy_get_rate()
1486 	if (src == CLK_PCIE_PHY_REF_SEL_PPLL) {  in rk3588_pciephy_get_rate()
2251 	u32 src, div;  in rk3588_clk_scmi_get_rate()  local
2255 		src = readl(BUSSCRU_BASE + RK3588_MODE_CON0) & 0x3;  in rk3588_clk_scmi_get_rate()
2256 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2258 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2263 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)) & 0x3000;  in rk3588_clk_scmi_get_rate()
2264 		src = src >> 12;  in rk3588_clk_scmi_get_rate()
2267 		if (src == 1)  in rk3588_clk_scmi_get_rate()
2269 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2274 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)) & 0x0020;  in rk3588_clk_scmi_get_rate()
2276 		if (src)  in rk3588_clk_scmi_get_rate()
2281 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(1)) & 0xc000;  in rk3588_clk_scmi_get_rate()
2282 		src = src >> 14;  in rk3588_clk_scmi_get_rate()
2283 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2285 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2287 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2292 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(1)) & 0x0c00;  in rk3588_clk_scmi_get_rate()
2293 		src = src >> 10;  in rk3588_clk_scmi_get_rate()
2294 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2296 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2298 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2303 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(1)) & 0x3000;  in rk3588_clk_scmi_get_rate()
2304 		src = src >> 12;  in rk3588_clk_scmi_get_rate()
2305 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2307 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2309 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2314 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(2)) & 0x00c0;  in rk3588_clk_scmi_get_rate()
2315 		src = src >> 6;  in rk3588_clk_scmi_get_rate()
2316 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2318 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2320 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2325 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(2)) & 0x0300;  in rk3588_clk_scmi_get_rate()
2326 		src = src >> 8;  in rk3588_clk_scmi_get_rate()
2327 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2329 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2331 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2339 		src = readl(SCRU_BASE + RK3588_CLKSEL_CON(1)) & 0x000c;  in rk3588_clk_scmi_get_rate()
2340 		src = src >> 2;  in rk3588_clk_scmi_get_rate()
2341 		if (src == 0)  in rk3588_clk_scmi_get_rate()
2343 		else if (src == 1)  in rk3588_clk_scmi_get_rate()
2345 		else if (src == 2)  in rk3588_clk_scmi_get_rate()
2356 	u32 src, div;  in rk3588_clk_scmi_set_rate()  local
2370 			src = 1;  in rk3588_clk_scmi_set_rate()
2372 			src = 0;  in rk3588_clk_scmi_set_rate()
2377 		writel(BITS_WITH_WMASK(src, 0x3U, 0),  in rk3588_clk_scmi_set_rate()
2413 			src = 0;  in rk3588_clk_scmi_set_rate()
2415 			src = 1;  in rk3588_clk_scmi_set_rate()
2417 			src = 2;  in rk3588_clk_scmi_set_rate()
2419 			src = 3;  in rk3588_clk_scmi_set_rate()
2421 		writel(BITS_WITH_WMASK(src, 0x3U, 14),  in rk3588_clk_scmi_set_rate()
2426 			src = 0;  in rk3588_clk_scmi_set_rate()
2428 			src = 1;  in rk3588_clk_scmi_set_rate()
2430 			src = 2;  in rk3588_clk_scmi_set_rate()
2432 			src = 3;  in rk3588_clk_scmi_set_rate()
2434 		writel(BITS_WITH_WMASK(src, 0x3U, 10),  in rk3588_clk_scmi_set_rate()
2439 			src = 0;  in rk3588_clk_scmi_set_rate()
2441 			src = 1;  in rk3588_clk_scmi_set_rate()
2443 			src = 2;  in rk3588_clk_scmi_set_rate()
2445 			src = 3;  in rk3588_clk_scmi_set_rate()
2447 		writel(BITS_WITH_WMASK(src, 0x3U, 12),  in rk3588_clk_scmi_set_rate()
2452 			src = 0;  in rk3588_clk_scmi_set_rate()
2454 			src = 1;  in rk3588_clk_scmi_set_rate()
2456 			src = 2;  in rk3588_clk_scmi_set_rate()
2458 			src = 3;  in rk3588_clk_scmi_set_rate()
2460 		writel(BITS_WITH_WMASK(src, 0x3U, 6),  in rk3588_clk_scmi_set_rate()
2465 			src = 0;  in rk3588_clk_scmi_set_rate()
2467 			src = 1;  in rk3588_clk_scmi_set_rate()
2469 			src = 2;  in rk3588_clk_scmi_set_rate()
2471 			src = 3;  in rk3588_clk_scmi_set_rate()
2473 		writel(BITS_WITH_WMASK(src, 0x3U, 8),  in rk3588_clk_scmi_set_rate()
2481 			src = 0;  in rk3588_clk_scmi_set_rate()
2483 			src = 1;  in rk3588_clk_scmi_set_rate()
2485 			src = 2;  in rk3588_clk_scmi_set_rate()
2487 			src = 3;  in rk3588_clk_scmi_set_rate()
2488 		writel(BITS_WITH_WMASK(src, 0x3U, 2),  in rk3588_clk_scmi_set_rate()