Lines Matching full:else
163 else if (sel == ACLK_CENTER_ROOT_SEL_400M) in rk3588_center_get_clk()
165 else if (sel == ACLK_CENTER_ROOT_SEL_200M) in rk3588_center_get_clk()
167 else in rk3588_center_get_clk()
176 else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M) in rk3588_center_get_clk()
178 else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M) in rk3588_center_get_clk()
180 else in rk3588_center_get_clk()
189 else if (sel == HCLK_CENTER_ROOT_SEL_200M) in rk3588_center_get_clk()
191 else if (sel == HCLK_CENTER_ROOT_SEL_100M) in rk3588_center_get_clk()
193 else in rk3588_center_get_clk()
202 else if (sel == PCLK_CENTER_ROOT_SEL_100M) in rk3588_center_get_clk()
204 else if (sel == PCLK_CENTER_ROOT_SEL_50M) in rk3588_center_get_clk()
206 else in rk3588_center_get_clk()
226 else if (rate >= 396 * MHz) in rk3588_center_set_clk()
228 else if (rate >= 200 * MHz) in rk3588_center_set_clk()
230 else in rk3588_center_set_clk()
239 else if (rate >= 250 * MHz) in rk3588_center_set_clk()
241 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
243 else in rk3588_center_set_clk()
252 else if (rate >= 198 * MHz) in rk3588_center_set_clk()
254 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
256 else in rk3588_center_set_clk()
265 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
267 else if (rate >= 50 * MHz) in rk3588_center_set_clk()
269 else in rk3588_center_set_clk()
297 else in rk3588_top_get_clk()
308 else in rk3588_top_get_clk()
316 else if (sel == PCLK_TOP_ROOT_SEL_50M) in rk3588_top_get_clk()
318 else in rk3588_top_get_clk()
339 } else { in rk3588_top_set_clk()
364 else if (rate == 50 * MHz) in rk3588_top_set_clk()
366 else in rk3588_top_set_clk()
428 else in rk3588_i2c_get_clk()
442 else in rk3588_i2c_set_clk()
536 else if (rate >= 140 * MHz) in rk3588_spi_set_clk()
538 else in rk3588_spi_set_clk()
620 else if (rate >= 50 * MHz) in rk3588_pwm_set_clk()
622 else in rk3588_pwm_set_clk()
666 else in rk3588_adc_get_clk()
677 else in rk3588_adc_get_clk()
703 } else { in rk3588_adc_set_clk()
726 } else { in rk3588_adc_set_clk()
757 else if (sel == CCLK_SDIO_SRC_SEL_CPLL) in rk3588_mmc_get_clk()
759 else in rk3588_mmc_get_clk()
769 else if (sel == CCLK_EMMC_SEL_CPLL) in rk3588_mmc_get_clk()
771 else in rk3588_mmc_get_clk()
781 else in rk3588_mmc_get_clk()
791 else if (sel == SCLK_SFC_SEL_CPLL) in rk3588_mmc_get_clk()
793 else in rk3588_mmc_get_clk()
803 else in rk3588_mmc_get_clk()
824 } else if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
827 } else { in rk3588_mmc_set_clk()
836 } else { in rk3588_mmc_set_clk()
845 } else { in rk3588_mmc_set_clk()
960 else if (sel == ACLK_VOP_ROOT_SEL_CPLL) in rk3588_aclk_vop_get_clk()
962 else if (sel == ACLK_VOP_ROOT_SEL_AUPLL) in rk3588_aclk_vop_get_clk()
964 else if (sel == ACLK_VOP_ROOT_SEL_NPLL) in rk3588_aclk_vop_get_clk()
966 else in rk3588_aclk_vop_get_clk()
975 else if (sel == ACLK_VOP_LOW_ROOT_SEL_200M) in rk3588_aclk_vop_get_clk()
977 else if (sel == ACLK_VOP_LOW_ROOT_SEL_100M) in rk3588_aclk_vop_get_clk()
979 else in rk3588_aclk_vop_get_clk()
986 else if (sel == HCLK_VOP_ROOT_SEL_100M) in rk3588_aclk_vop_get_clk()
988 else if (sel == HCLK_VOP_ROOT_SEL_50M) in rk3588_aclk_vop_get_clk()
990 else in rk3588_aclk_vop_get_clk()
1009 } else if (rate >= 750 * MHz) { in rk3588_aclk_vop_set_clk()
1012 } else if (rate >= 700 * MHz) { in rk3588_aclk_vop_set_clk()
1015 } else if (!(priv->cpll_hz % rate)) { in rk3588_aclk_vop_set_clk()
1018 } else { in rk3588_aclk_vop_set_clk()
1031 else if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1033 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1035 else in rk3588_aclk_vop_set_clk()
1044 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1046 else if (rate == 50 * MHz) in rk3588_aclk_vop_set_clk()
1048 else in rk3588_aclk_vop_set_clk()
1096 else if (sel == DCLK_VOP_SRC_SEL_V0PLL) in rk3588_dclk_vop_get_clk()
1099 else if (sel == DCLK_VOP_SRC_SEL_GPLL) in rk3588_dclk_vop_get_clk()
1101 else in rk3588_dclk_vop_get_clk()
1166 } else { in rk3588_dclk_vop_set_clk()
1177 } else { in rk3588_dclk_vop_set_clk()
1215 } else { in rk3588_dclk_vop_set_clk()
1244 else if (sel == CLK_DSIHOST_SEL_CPLL) in rk3588_clk_csihost_get_clk()
1246 else if (sel == CLK_DSIHOST_SEL_V0PLL) in rk3588_clk_csihost_get_clk()
1248 else in rk3588_clk_csihost_get_clk()
1366 else in rk3588_uart_get_rate()
1371 } else if (src == CLK_UART_SEL_FRAC) { in rk3588_uart_get_rate()
1378 } else { in rk3588_uart_get_rate()
1394 } else if (priv->cpll_hz % rate == 0) { in rk3588_uart_set_rate()
1398 } else if (rate == OSC_HZ) { in rk3588_uart_set_rate()
1402 } else { in rk3588_uart_set_rate()
1488 } else { in rk3588_pciephy_get_rate()
1502 } else { in rk3588_pciephy_set_rate()
1869 else in rk3588_mmc_get_phase()
1971 else if (parent->id == PLL_GPLL) in rk3588_dclk_vop_set_parent()
1973 else if (parent->id == PLL_CPLL) in rk3588_dclk_vop_set_parent()
1975 else in rk3588_dclk_vop_set_parent()
1998 else if (!strcmp(clock_dev_name, "hdmiphypll_clk1")) in rk3588_dclk_vop_set_parent()
2000 else in rk3588_dclk_vop_set_parent()
2008 else if (!strcmp(clock_dev_name, "hdmiphypll_clk1")) in rk3588_dclk_vop_set_parent()
2010 else in rk3588_dclk_vop_set_parent()
2018 else if (!strcmp(clock_dev_name, "hdmiphypll_clk1")) in rk3588_dclk_vop_set_parent()
2020 else in rk3588_dclk_vop_set_parent()
2142 } else { in rk3588_clk_probe()
2168 else in rk3588_clk_probe()
2195 } else { in rk3588_clk_bind()
2208 } else { in rk3588_clk_bind()
2258 else if (src == 1) in rk3588_clk_scmi_get_rate()
2260 else in rk3588_clk_scmi_get_rate()
2269 else if (src == 2) in rk3588_clk_scmi_get_rate()
2271 else in rk3588_clk_scmi_get_rate()
2278 else in rk3588_clk_scmi_get_rate()
2285 else if (src == 1) in rk3588_clk_scmi_get_rate()
2287 else if (src == 2) in rk3588_clk_scmi_get_rate()
2289 else in rk3588_clk_scmi_get_rate()
2296 else if (src == 1) in rk3588_clk_scmi_get_rate()
2298 else if (src == 2) in rk3588_clk_scmi_get_rate()
2300 else in rk3588_clk_scmi_get_rate()
2307 else if (src == 1) in rk3588_clk_scmi_get_rate()
2309 else if (src == 2) in rk3588_clk_scmi_get_rate()
2311 else in rk3588_clk_scmi_get_rate()
2318 else if (src == 1) in rk3588_clk_scmi_get_rate()
2320 else if (src == 2) in rk3588_clk_scmi_get_rate()
2322 else in rk3588_clk_scmi_get_rate()
2329 else if (src == 1) in rk3588_clk_scmi_get_rate()
2331 else if (src == 2) in rk3588_clk_scmi_get_rate()
2333 else in rk3588_clk_scmi_get_rate()
2343 else if (src == 1) in rk3588_clk_scmi_get_rate()
2345 else if (src == 2) in rk3588_clk_scmi_get_rate()
2347 else in rk3588_clk_scmi_get_rate()
2371 else in rk3588_clk_scmi_set_rate()
2386 } else if ((SPLL_RATE % rate) == 0) { in rk3588_clk_scmi_set_rate()
2391 } else { in rk3588_clk_scmi_set_rate()
2404 } else { in rk3588_clk_scmi_set_rate()
2414 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2416 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2418 else in rk3588_clk_scmi_set_rate()
2427 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2429 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2431 else in rk3588_clk_scmi_set_rate()
2440 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2442 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2444 else in rk3588_clk_scmi_set_rate()
2453 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2455 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2457 else in rk3588_clk_scmi_set_rate()
2466 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2468 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2470 else in rk3588_clk_scmi_set_rate()
2482 else if (rate >= 100 * MHz) in rk3588_clk_scmi_set_rate()
2484 else if (rate >= 50 * MHz) in rk3588_clk_scmi_set_rate()
2486 else in rk3588_clk_scmi_set_rate()
2557 else in soc_clk_dump()