Lines Matching refs:src_clk_div
221 int src_clk, src_clk_div; in rk3576_bus_set_clk() local
227 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_bus_set_clk()
230 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_bus_set_clk()
235 assert(src_clk_div - 1 <= 31); in rk3576_bus_set_clk()
241 (src_clk_div - 1) << ACLK_BUS_ROOT_DIV_SHIFT); in rk3576_bus_set_clk()
338 int src_clk, src_clk_div; in rk3576_top_set_clk() local
344 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_top_set_clk()
347 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_top_set_clk()
349 assert(src_clk_div - 1 <= 31); in rk3576_top_set_clk()
355 (src_clk_div - 1) << ACLK_TOP_SEL_SHIFT); in rk3576_top_set_clk()
360 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_top_set_clk()
363 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_top_set_clk()
370 (src_clk_div - 1) << ACLK_TOP_MID_DIV_SHIFT); in rk3576_top_set_clk()
722 int src_clk_div; in rk3576_adc_set_clk() local
727 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3576_adc_set_clk()
728 assert(src_clk_div - 1 <= 255); in rk3576_adc_set_clk()
734 (src_clk_div - 1) << in rk3576_adc_set_clk()
737 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_adc_set_clk()
738 assert(src_clk_div - 1 <= 255); in rk3576_adc_set_clk()
744 (src_clk_div - 1) << in rk3576_adc_set_clk()
749 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3576_adc_set_clk()
750 assert(src_clk_div - 1 <= 255); in rk3576_adc_set_clk()
753 (src_clk_div - 1) << in rk3576_adc_set_clk()