Lines Matching refs:src_clk
221 int src_clk, src_clk_div; in rk3576_bus_set_clk() local
226 src_clk = ACLK_BUS_ROOT_SEL_CPLL; in rk3576_bus_set_clk()
229 src_clk = ACLK_BUS_ROOT_SEL_GPLL; in rk3576_bus_set_clk()
234 src_clk << ACLK_BUS_ROOT_SEL_SHIFT); in rk3576_bus_set_clk()
239 (src_clk << in rk3576_bus_set_clk()
245 src_clk = HCLK_BUS_ROOT_SEL_200M; in rk3576_bus_set_clk()
247 src_clk = HCLK_BUS_ROOT_SEL_100M; in rk3576_bus_set_clk()
249 src_clk = HCLK_BUS_ROOT_SEL_50M; in rk3576_bus_set_clk()
251 src_clk = HCLK_BUS_ROOT_SEL_OSC; in rk3576_bus_set_clk()
254 src_clk << HCLK_BUS_ROOT_SEL_SHIFT); in rk3576_bus_set_clk()
258 src_clk = PCLK_BUS_ROOT_SEL_100M; in rk3576_bus_set_clk()
260 src_clk = PCLK_BUS_ROOT_SEL_50M; in rk3576_bus_set_clk()
262 src_clk = PCLK_BUS_ROOT_SEL_OSC; in rk3576_bus_set_clk()
265 src_clk << PCLK_BUS_ROOT_SEL_SHIFT); in rk3576_bus_set_clk()
338 int src_clk, src_clk_div; in rk3576_top_set_clk() local
343 src_clk = ACLK_TOP_SEL_CPLL; in rk3576_top_set_clk()
346 src_clk = ACLK_TOP_SEL_GPLL; in rk3576_top_set_clk()
353 (src_clk << in rk3576_top_set_clk()
359 src_clk = ACLK_TOP_MID_SEL_CPLL; in rk3576_top_set_clk()
362 src_clk = ACLK_TOP_MID_SEL_GPLL; in rk3576_top_set_clk()
374 src_clk = PCLK_TOP_SEL_100M; in rk3576_top_set_clk()
376 src_clk = PCLK_TOP_SEL_50M; in rk3576_top_set_clk()
378 src_clk = PCLK_TOP_SEL_OSC; in rk3576_top_set_clk()
381 src_clk << PCLK_TOP_SEL_SHIFT); in rk3576_top_set_clk()
385 src_clk = HCLK_TOP_SEL_200M; in rk3576_top_set_clk()
387 src_clk = HCLK_TOP_SEL_100M; in rk3576_top_set_clk()
389 src_clk = HCLK_TOP_SEL_50M; in rk3576_top_set_clk()
391 src_clk = HCLK_TOP_SEL_OSC; in rk3576_top_set_clk()
394 src_clk << HCLK_TOP_SEL_SHIFT); in rk3576_top_set_clk()
471 int src_clk; in rk3576_i2c_set_clk() local
474 src_clk = CLK_I2C_SEL_200M; in rk3576_i2c_set_clk()
476 src_clk = CLK_I2C_SEL_100M; in rk3576_i2c_set_clk()
478 src_clk = CLK_I2C_SEL_50M; in rk3576_i2c_set_clk()
480 src_clk = CLK_I2C_SEL_OSC; in rk3576_i2c_set_clk()
485 src_clk << CLK_I2C0_SEL_SHIFT); in rk3576_i2c_set_clk()
489 src_clk << CLK_I2C1_SEL_SHIFT); in rk3576_i2c_set_clk()
493 src_clk << CLK_I2C2_SEL_SHIFT); in rk3576_i2c_set_clk()
497 src_clk << CLK_I2C3_SEL_SHIFT); in rk3576_i2c_set_clk()
501 src_clk << CLK_I2C4_SEL_SHIFT); in rk3576_i2c_set_clk()
505 src_clk << CLK_I2C5_SEL_SHIFT); in rk3576_i2c_set_clk()
509 src_clk << CLK_I2C6_SEL_SHIFT); in rk3576_i2c_set_clk()
513 src_clk << CLK_I2C7_SEL_SHIFT); in rk3576_i2c_set_clk()
517 src_clk << CLK_I2C8_SEL_SHIFT); in rk3576_i2c_set_clk()
520 src_clk << CLK_I2C9_SEL_SHIFT); in rk3576_i2c_set_clk()
577 int src_clk; in rk3576_spi_set_clk() local
580 src_clk = CLK_SPI_SEL_200M; in rk3576_spi_set_clk()
582 src_clk = CLK_SPI_SEL_100M; in rk3576_spi_set_clk()
584 src_clk = CLK_SPI_SEL_50M; in rk3576_spi_set_clk()
586 src_clk = CLK_SPI_SEL_OSC; in rk3576_spi_set_clk()
592 src_clk << CLK_SPI0_SEL_SHIFT); in rk3576_spi_set_clk()
597 src_clk << CLK_SPI1_SEL_SHIFT); in rk3576_spi_set_clk()
602 src_clk << CLK_SPI2_SEL_SHIFT); in rk3576_spi_set_clk()
607 src_clk << CLK_SPI3_SEL_SHIFT); in rk3576_spi_set_clk()
612 src_clk << CLK_SPI4_SEL_SHIFT); in rk3576_spi_set_clk()
659 int src_clk; in rk3576_pwm_set_clk() local
662 src_clk = CLK_PWM_SEL_100M; in rk3576_pwm_set_clk()
664 src_clk = CLK_PWM_SEL_50M; in rk3576_pwm_set_clk()
666 src_clk = CLK_PWM_SEL_OSC; in rk3576_pwm_set_clk()
672 src_clk << CLK_PWM1_SEL_SHIFT); in rk3576_pwm_set_clk()
677 src_clk << CLK_PWM2_SEL_SHIFT); in rk3576_pwm_set_clk()
682 src_clk << CLK_PMU1PWM_SEL_SHIFT); in rk3576_pwm_set_clk()
863 int src_clk, div = 0; in rk3576_mmc_set_clk() local
875 src_clk = SCLK_FSPI_SEL_OSC; in rk3576_mmc_set_clk()
878 src_clk = SCLK_FSPI_SEL_CPLL; in rk3576_mmc_set_clk()
881 src_clk = SCLK_FSPI_SEL_GPLL; in rk3576_mmc_set_clk()
887 src_clk = BCLK_EMMC_SEL_200M; in rk3576_mmc_set_clk()
889 src_clk = BCLK_EMMC_SEL_100M; in rk3576_mmc_set_clk()
891 src_clk = BCLK_EMMC_SEL_50M; in rk3576_mmc_set_clk()
893 src_clk = BCLK_EMMC_SEL_OSC; in rk3576_mmc_set_clk()
897 src_clk = DCLK_DECOM_SEL_SPLL; in rk3576_mmc_set_clk()
900 src_clk = DCLK_DECOM_SEL_GPLL; in rk3576_mmc_set_clk()
914 (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) | in rk3576_mmc_set_clk()
922 (src_clk << CCLK_SDMMC0_SRC_SEL_SHIFT) | in rk3576_mmc_set_clk()
930 (src_clk << CCLK_EMMC_SEL_SHIFT) | in rk3576_mmc_set_clk()
937 (src_clk << SCLK_FSPI_SEL_SHIFT) | in rk3576_mmc_set_clk()
944 (src_clk << SCLK_FSPI_SEL_SHIFT) | in rk3576_mmc_set_clk()
950 src_clk << BCLK_EMMC_SEL_SHIFT); in rk3576_mmc_set_clk()
956 (src_clk << DCLK_DECOM_SEL_SHIFT) | in rk3576_mmc_set_clk()
1047 int src_clk, div; in rk3576_aclk_vop_set_clk() local
1053 src_clk = ACLK_VOP_ROOT_SEL_SPLL; in rk3576_aclk_vop_set_clk()
1056 src_clk = ACLK_VOP_ROOT_SEL_CPLL; in rk3576_aclk_vop_set_clk()
1059 src_clk = ACLK_VOP_ROOT_SEL_GPLL; in rk3576_aclk_vop_set_clk()
1065 (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) | in rk3576_aclk_vop_set_clk()
1070 src_clk = ACLK_VO0_ROOT_SEL_CPLL; in rk3576_aclk_vop_set_clk()
1073 src_clk = ACLK_VO0_ROOT_SEL_GPLL; in rk3576_aclk_vop_set_clk()
1079 (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) | in rk3576_aclk_vop_set_clk()
1084 src_clk = ACLK_VO0_ROOT_SEL_CPLL; in rk3576_aclk_vop_set_clk()
1087 src_clk = ACLK_VO0_ROOT_SEL_GPLL; in rk3576_aclk_vop_set_clk()
1093 (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) | in rk3576_aclk_vop_set_clk()
1098 src_clk = HCLK_VOP_ROOT_SEL_200M; in rk3576_aclk_vop_set_clk()
1100 src_clk = HCLK_VOP_ROOT_SEL_100M; in rk3576_aclk_vop_set_clk()
1102 src_clk = HCLK_VOP_ROOT_SEL_50M; in rk3576_aclk_vop_set_clk()
1104 src_clk = HCLK_VOP_ROOT_SEL_OSC; in rk3576_aclk_vop_set_clk()
1107 src_clk << HCLK_VOP_ROOT_SEL_SHIFT); in rk3576_aclk_vop_set_clk()
1111 src_clk = PCLK_VOP_ROOT_SEL_100M; in rk3576_aclk_vop_set_clk()
1113 src_clk = PCLK_VOP_ROOT_SEL_50M; in rk3576_aclk_vop_set_clk()
1115 src_clk = PCLK_VOP_ROOT_SEL_OSC; in rk3576_aclk_vop_set_clk()
1118 src_clk << PCLK_VOP_ROOT_SEL_SHIFT); in rk3576_aclk_vop_set_clk()