2224 	ulong ret = 0;  in rk3576_clk_set_rate()  local
2237 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru,  in rk3576_clk_set_rate()
2243 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru,  in rk3576_clk_set_rate()
2249 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], priv->cru,  in rk3576_clk_set_rate()
2255 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[AUPLL], priv->cru,  in rk3576_clk_set_rate()
2261 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[PPLL], priv->cru,  in rk3576_clk_set_rate()
2269 		ret = rk3576_bus_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2275 		ret = rk3576_top_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2287 		ret = rk3576_i2c_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2294 		ret = rk3576_spi_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2299 		ret = rk3576_pwm_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2303 		ret = rk3576_adc_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2315 		ret = rk3576_mmc_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2318 		ret = OSC_HZ;  in rk3576_clk_set_rate()
2327 		ret = rk3576_aclk_vop_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2335 		ret = rk3576_dclk_vop_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2343 		ret = rk3576_gmac_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2348 		ret = rk3576_uart_frac_set_rate(priv, clk->id, rate);  in rk3576_clk_set_rate()
2362 		ret = rk3576_uart_set_rate(priv, clk->id, rate);  in rk3576_clk_set_rate()
2365 		ret = rk3576_clk_csihost_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2369 		ret = rk3576_dclk_ebc_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2374 		ret = rk3576_ref_clkout_set_clk(priv, clk->id, rate);  in rk3576_clk_set_rate()
2381 	return ret;  in rk3576_clk_set_rate()
2516 	int ret;  in rk3576_clk_init()  local
2521 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru,  in rk3576_clk_init()
2523 		if (!ret)  in rk3576_clk_init()
2527 		ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru,  in rk3576_clk_init()
2529 		if (!ret)  in rk3576_clk_init()
2541 	int ret;  in rk3576_clk_probe()  local
2571 			ret = rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru,  in rk3576_clk_probe()
2604 	ret = rockchip_get_scmi_clk(&clk.dev);  in rk3576_clk_probe()
2605 	if (ret) {  in rk3576_clk_probe()
2606 		printf("Failed to get scmi clk dev, ret=%d\n", ret);  in rk3576_clk_probe()
2607 		return ret;  in rk3576_clk_probe()
2611 		ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);  in rk3576_clk_probe()
2612 		if (ret < 0) {  in rk3576_clk_probe()
2613 			printf("Failed to set cpubl, ret=%d\n", ret);  in rk3576_clk_probe()
2620 	ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);  in rk3576_clk_probe()
2621 	if (ret < 0)  in rk3576_clk_probe()
2622 		printf("Failed to set cpub, ret=%d\n", ret);  in rk3576_clk_probe()
2627 	ret = clk_set_defaults(dev);  in rk3576_clk_probe()
2628 	if (ret)  in rk3576_clk_probe()
2629 		debug("%s clk_set_defaults failed %d\n", __func__, ret);  in rk3576_clk_probe()
2647 	int ret;  in rk3576_clk_bind()  local
2653 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",  in rk3576_clk_bind()
2655 	if (ret) {  in rk3576_clk_bind()
2656 		debug("Warning: No sysreset driver: ret=%d\n", ret);  in rk3576_clk_bind()
2666 	ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",  in rk3576_clk_bind()
2668 	if (ret) {  in rk3576_clk_bind()
2669 		debug("Warning: No rockchip reset driver: ret=%d\n", ret);  in rk3576_clk_bind()
2712 	int i, ret;  in soc_clk_dump()  local
2714 	ret = uclass_get_device_by_driver(UCLASS_CLK,  in soc_clk_dump()
2717 	if (ret) {  in soc_clk_dump()
2719 		return ret;  in soc_clk_dump()
2735 				ret = clk_request(cru_dev, &clk);  in soc_clk_dump()
2736 			if (ret < 0)  in soc_clk_dump()
2737 				return ret;  in soc_clk_dump()