Lines Matching full:else
48 #else
183 else in rk3576_bus_get_clk()
192 else if (sel == HCLK_BUS_ROOT_SEL_100M) in rk3576_bus_get_clk()
194 else if (sel == HCLK_BUS_ROOT_SEL_50M) in rk3576_bus_get_clk()
196 else in rk3576_bus_get_clk()
205 else if (sel == PCLK_BUS_ROOT_SEL_50M) in rk3576_bus_get_clk()
207 else in rk3576_bus_get_clk()
228 } else { in rk3576_bus_set_clk()
246 else if (rate >= 99 * MHz) in rk3576_bus_set_clk()
248 else if (rate >= 50 * MHz) in rk3576_bus_set_clk()
250 else in rk3576_bus_set_clk()
259 else if (rate >= 50 * MHz) in rk3576_bus_set_clk()
261 else in rk3576_bus_set_clk()
289 else if (sel == ACLK_TOP_SEL_AUPLL) in rk3576_top_get_clk()
291 else in rk3576_top_get_clk()
302 else in rk3576_top_get_clk()
310 else if (sel == PCLK_TOP_SEL_50M) in rk3576_top_get_clk()
312 else in rk3576_top_get_clk()
320 else if (sel == HCLK_TOP_SEL_100M) in rk3576_top_get_clk()
322 else if (sel == HCLK_TOP_SEL_50M) in rk3576_top_get_clk()
324 else in rk3576_top_get_clk()
345 } else { in rk3576_top_set_clk()
361 } else { in rk3576_top_set_clk()
375 else if (rate >= 50 * MHz) in rk3576_top_set_clk()
377 else in rk3576_top_set_clk()
386 else if (rate >= 99 * MHz) in rk3576_top_set_clk()
388 else if (rate >= 50 * MHz) in rk3576_top_set_clk()
390 else in rk3576_top_set_clk()
457 else if (sel == CLK_I2C_SEL_100M) in rk3576_i2c_get_clk()
459 else if (sel == CLK_I2C_SEL_50M) in rk3576_i2c_get_clk()
461 else in rk3576_i2c_get_clk()
475 else if (rate >= 99 * MHz) in rk3576_i2c_set_clk()
479 else in rk3576_i2c_set_clk()
581 else if (rate >= 99 * MHz) in rk3576_spi_set_clk()
583 else if (rate >= 50 * MHz) in rk3576_spi_set_clk()
585 else in rk3576_spi_set_clk()
663 else if (rate >= 50 * MHz) in rk3576_pwm_set_clk()
665 else in rk3576_pwm_set_clk()
704 else in rk3576_adc_get_clk()
736 } else { in rk3576_adc_set_clk()
776 else if (sel == CCLK_SDIO_SRC_SEL_CPLL) in rk3576_mmc_get_clk()
778 else in rk3576_mmc_get_clk()
789 else if (sel == CCLK_SDMMC0_SRC_SEL_CPLL) in rk3576_mmc_get_clk()
791 else in rk3576_mmc_get_clk()
802 else if (sel == CCLK_EMMC_SEL_CPLL) in rk3576_mmc_get_clk()
804 else in rk3576_mmc_get_clk()
813 else if (sel == BCLK_EMMC_SEL_100M) in rk3576_mmc_get_clk()
815 else if (sel == BCLK_EMMC_SEL_50M) in rk3576_mmc_get_clk()
817 else in rk3576_mmc_get_clk()
827 else if (sel == SCLK_FSPI_SEL_CPLL) in rk3576_mmc_get_clk()
829 else in rk3576_mmc_get_clk()
839 else if (sel == SCLK_FSPI_SEL_CPLL) in rk3576_mmc_get_clk()
841 else in rk3576_mmc_get_clk()
850 else in rk3576_mmc_get_clk()
877 } else if (!(priv->cpll_hz % rate)) { in rk3576_mmc_set_clk()
880 } else { in rk3576_mmc_set_clk()
888 else if (rate >= 99 * MHz) in rk3576_mmc_set_clk()
890 else if (rate >= 50 * MHz) in rk3576_mmc_set_clk()
892 else in rk3576_mmc_set_clk()
899 } else { in rk3576_mmc_set_clk()
982 else if (sel == ACLK_VOP_ROOT_SEL_CPLL) in rk3576_aclk_vop_get_clk()
984 else if (sel == ACLK_VOP_ROOT_SEL_AUPLL) in rk3576_aclk_vop_get_clk()
986 else if (sel == ACLK_VOP_ROOT_SEL_SPLL) in rk3576_aclk_vop_get_clk()
988 else if (sel == ACLK_VOP_ROOT_SEL_LPLL) in rk3576_aclk_vop_get_clk()
997 else if (sel == ACLK_VO0_ROOT_SEL_CPLL) in rk3576_aclk_vop_get_clk()
999 else if (sel == ACLK_VO0_ROOT_SEL_LPLL) in rk3576_aclk_vop_get_clk()
1001 else if (sel == ACLK_VO0_ROOT_SEL_BPLL) in rk3576_aclk_vop_get_clk()
1010 else if (sel == ACLK_VO0_ROOT_SEL_CPLL) in rk3576_aclk_vop_get_clk()
1012 else if (sel == ACLK_VO0_ROOT_SEL_LPLL) in rk3576_aclk_vop_get_clk()
1014 else if (sel == ACLK_VO0_ROOT_SEL_BPLL) in rk3576_aclk_vop_get_clk()
1022 else if (sel == HCLK_VOP_ROOT_SEL_100M) in rk3576_aclk_vop_get_clk()
1024 else if (sel == HCLK_VOP_ROOT_SEL_50M) in rk3576_aclk_vop_get_clk()
1026 else in rk3576_aclk_vop_get_clk()
1033 else if (sel == PCLK_VOP_ROOT_SEL_50M) in rk3576_aclk_vop_get_clk()
1035 else in rk3576_aclk_vop_get_clk()
1055 } else if (!(priv->cpll_hz % rate)) { in rk3576_aclk_vop_set_clk()
1058 } else { in rk3576_aclk_vop_set_clk()
1072 } else { in rk3576_aclk_vop_set_clk()
1086 } else { in rk3576_aclk_vop_set_clk()
1099 else if (rate == 100 * MHz) in rk3576_aclk_vop_set_clk()
1101 else if (rate == 50 * MHz) in rk3576_aclk_vop_set_clk()
1103 else in rk3576_aclk_vop_set_clk()
1112 else if (rate == 50 * MHz) in rk3576_aclk_vop_set_clk()
1114 else in rk3576_aclk_vop_set_clk()
1158 else if (sel == DCLK_VOP_SRC_SEL_BPLL) in rk3576_dclk_vop_get_clk()
1160 else if (sel == DCLK_VOP_SRC_SEL_LPLL) in rk3576_dclk_vop_get_clk()
1162 else if (sel == DCLK_VOP_SRC_SEL_GPLL) in rk3576_dclk_vop_get_clk()
1164 else in rk3576_dclk_vop_get_clk()
1221 } else { in rk3576_dclk_vop_set_clk()
1234 } else { in rk3576_dclk_vop_set_clk()
1275 } else { in rk3576_dclk_vop_set_clk()
1300 else if (sel == CLK_DSIHOST0_SEL_BPLL) in rk3576_clk_csihost_get_clk()
1302 else if (sel == CLK_DSIHOST0_SEL_LPLL) in rk3576_clk_csihost_get_clk()
1304 else if (sel == CLK_DSIHOST0_SEL_GPLL) in rk3576_clk_csihost_get_clk()
1306 else if (sel == CLK_DSIHOST0_SEL_SPLL) in rk3576_clk_csihost_get_clk()
1308 else in rk3576_clk_csihost_get_clk()
1374 } else { in rk3576_clk_csihost_set_clk()
1394 else if (sel == DCLK_EBC_SEL_VPLL) in rk3576_dclk_ebc_get_clk()
1396 else if (sel == DCLK_EBC_SEL_AUPLL) in rk3576_dclk_ebc_get_clk()
1398 else if (sel == DCLK_EBC_SEL_LPLL) in rk3576_dclk_ebc_get_clk()
1400 else if (sel == DCLK_EBC_SEL_GPLL) in rk3576_dclk_ebc_get_clk()
1402 else if (sel == DCLK_EBC_SEL_FRAC_SRC) in rk3576_dclk_ebc_get_clk()
1404 else in rk3576_dclk_ebc_get_clk()
1413 else if (sel == DCLK_EBC_FRAC_SRC_SEL_CPLL) in rk3576_dclk_ebc_get_clk()
1415 else if (sel == DCLK_EBC_FRAC_SRC_SEL_VPLL) in rk3576_dclk_ebc_get_clk()
1417 else if (sel == DCLK_EBC_FRAC_SRC_SEL_AUPLL) in rk3576_dclk_ebc_get_clk()
1419 else in rk3576_dclk_ebc_get_clk()
1453 } else { in rk3576_dclk_ebc_set_clk()
1468 } else if (sel == DCLK_EBC_SEL_FRAC_SRC) { in rk3576_dclk_ebc_set_clk()
1474 } else { in rk3576_dclk_ebc_set_clk()
1516 } else { in rk3576_dclk_ebc_set_clk()
1534 else in rk3576_dclk_ebc_set_clk()
1571 else if (src == CLK_GMAC0_PTP_SEL_CPLL) in rk3576_gmac_get_clk()
1573 else in rk3576_gmac_get_clk()
1583 else if (src == CLK_GMAC1_PTP_SEL_CPLL) in rk3576_gmac_get_clk()
1585 else in rk3576_gmac_get_clk()
1615 } else if (!(priv->gpll_hz % rate)) { in rk3576_gmac_set_clk()
1618 } else { in rk3576_gmac_set_clk()
1632 } else if (!(priv->gpll_hz % rate)) { in rk3576_gmac_set_clk()
1635 } else { in rk3576_gmac_set_clk()
1685 else if (p_src == CLK_UART_SRC_SEL_CPLL) in rk3576_uart_frac_get_rate()
1687 else if (p_src == CLK_UART_SRC_SEL_AUPLL) in rk3576_uart_frac_get_rate()
1689 else in rk3576_uart_frac_get_rate()
1710 } else if (rate == OSC_HZ) { in rk3576_uart_frac_set_rate()
1713 } else { in rk3576_uart_frac_set_rate()
1725 else in rk3576_uart_frac_set_rate()
1813 } else { in rk3576_uart_get_rate()
1819 else if (src == CLK_UART_SEL_CPLL) in rk3576_uart_get_rate()
1821 else if (src == CLK_UART_SEL_AUPLL) in rk3576_uart_get_rate()
1823 else if (src == CLK_UART_SEL_FRAC0) in rk3576_uart_get_rate()
1825 else if (src == CLK_UART_SEL_FRAC1) in rk3576_uart_get_rate()
1827 else if (src == CLK_UART_SEL_FRAC2) in rk3576_uart_get_rate()
1829 else in rk3576_uart_get_rate()
1844 } else if (!(priv->cpll_hz % rate)) { in rk3576_uart_set_rate()
1847 } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0) % rate)) { in rk3576_uart_set_rate()
1850 } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1) % rate)) { in rk3576_uart_set_rate()
1853 } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2) % rate)) { in rk3576_uart_set_rate()
1856 } else if (!(OSC_HZ % rate)) { in rk3576_uart_set_rate()
1871 } else { in rk3576_uart_set_rate()
1949 else if (src == REF_CLK0_OUT_PLL_SEL_CPLL) in rk3576_ref_clkout_get_clk()
1951 else if (src == REF_CLK0_OUT_PLL_SEL_SPLL) in rk3576_ref_clkout_get_clk()
1953 else if (src == REF_CLK0_OUT_PLL_SEL_AUPLL) in rk3576_ref_clkout_get_clk()
1955 else if (src == REF_CLK0_OUT_PLL_SEL_LPLL) in rk3576_ref_clkout_get_clk()
1957 else in rk3576_ref_clkout_get_clk()
2026 } else { in rk3576_ref_clkout_set_clk()
2045 else if (src == 2) in rk3576_ufs_ref_get_rate()
2047 else in rk3576_ufs_ref_get_rate()
2395 else if (parent->id == PLL_GPLL) in rk3576_dclk_vop_set_parent()
2397 else if (parent->id == PLL_CPLL) in rk3576_dclk_vop_set_parent()
2399 else if (parent->id == PLL_BPLL) in rk3576_dclk_vop_set_parent()
2401 else in rk3576_dclk_vop_set_parent()
2420 else in rk3576_dclk_vop_set_parent()
2428 else in rk3576_dclk_vop_set_parent()
2436 else in rk3576_dclk_vop_set_parent()
2444 else if (parent->id == PLL_CPLL) in rk3576_dclk_vop_set_parent()
2446 else if (parent->id == PLL_VPLL) in rk3576_dclk_vop_set_parent()
2448 else if (parent->id == PLL_AUPLL) in rk3576_dclk_vop_set_parent()
2450 else if (parent->id == PLL_LPLL) in rk3576_dclk_vop_set_parent()
2452 else if (parent->id == DCLK_EBC_FRAC_SRC) in rk3576_dclk_vop_set_parent()
2454 else in rk3576_dclk_vop_set_parent()
2475 else if (!strcmp(clock_dev_name, "xin24m")) in rk3576_ufs_ref_set_parent()
2477 else in rk3576_ufs_ref_set_parent()
2614 } else { in rk3576_clk_probe()
2630 else in rk3576_clk_probe()
2657 } else { in rk3576_clk_bind()
2670 } else { in rk3576_clk_bind()
2744 else in soc_clk_dump()