266 	int src_clk_div;  in rk3568_i2c_set_pmuclk()  local
268 	src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);  in rk3568_i2c_set_pmuclk()
269 	assert(src_clk_div - 1 <= 127);  in rk3568_i2c_set_pmuclk()
274 			     (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT);  in rk3568_i2c_set_pmuclk()
310 	int src_clk_div;  in rk3568_pwm_set_pmuclk()  local
321 			src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);  in rk3568_pwm_set_pmuclk()
322 			assert(src_clk_div - 1 <= 127);  in rk3568_pwm_set_pmuclk()
326 				     (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT);  in rk3568_pwm_set_pmuclk()
356 	int src_clk_div;  in rk3568_pmu_set_pmuclk()  local
358 	src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate);  in rk3568_pmu_set_pmuclk()
359 	assert(src_clk_div - 1 <= 31);  in rk3568_pmu_set_pmuclk()
364 		     ((src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT));  in rk3568_pmu_set_pmuclk()
1261 	int src_clk_div;  in rk3568_adc_set_clk()  local
1269 			src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3568_adc_set_clk()
1270 			assert(src_clk_div - 1 <= 7);  in rk3568_adc_set_clk()
1276 				     (src_clk_div - 1) <<  in rk3568_adc_set_clk()
1279 			src_clk_div = DIV_ROUND_UP(100 * MHz, rate);  in rk3568_adc_set_clk()
1280 			assert(src_clk_div - 1 <= 7);  in rk3568_adc_set_clk()
1286 				     (src_clk_div - 1) <<  in rk3568_adc_set_clk()
1292 			src_clk_div = DIV_ROUND_UP(prate, rate);  in rk3568_adc_set_clk()
1293 			assert(src_clk_div - 1 <= 128);  in rk3568_adc_set_clk()
1296 				     (src_clk_div - 1) << CLK_TSADC_DIV_SHIFT);  in rk3568_adc_set_clk()
1763 	int src_clk_div, src_clk_mux;  in rk3568_aclk_vop_set_clk()  local
1766 		src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3568_aclk_vop_set_clk()
1769 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3568_aclk_vop_set_clk()
1772 	assert(src_clk_div - 1 <= 31);  in rk3568_aclk_vop_set_clk()
1776 		     (src_clk_div - 1) << ACLK_VOP_PRE_DIV_SHIFT);  in rk3568_aclk_vop_set_clk()
2118 	int src_clk_div;  in rk3568_ebc_set_clk()  local
2120 	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3568_ebc_set_clk()
2121 	assert(src_clk_div - 1 <= 31);  in rk3568_ebc_set_clk()
2124 		     (src_clk_div - 1) << CPLL_333M_DIV_SHIFT);  in rk3568_ebc_set_clk()
2172 	int src_clk_div, src, p_rate;  in rk3568_rkvdec_set_clk()  local
2183 		src_clk_div = DIV_ROUND_UP(p_rate, rate);  in rk3568_rkvdec_set_clk()
2184 		assert(src_clk_div - 1 <= 31);  in rk3568_rkvdec_set_clk()
2189 			     (src_clk_div - 1) << ACLK_RKVDEC_DIV_SHIFT);  in rk3568_rkvdec_set_clk()
2202 		src_clk_div = DIV_ROUND_UP(p_rate, rate);  in rk3568_rkvdec_set_clk()
2203 		assert(src_clk_div - 1 <= 31);  in rk3568_rkvdec_set_clk()
2208 			     (src_clk_div - 1) << CLK_RKVDEC_CORE_DIV_SHIFT);  in rk3568_rkvdec_set_clk()