Lines Matching refs:src_clk
778 int src_clk; in rk3568_bus_set_clk() local
783 src_clk = ACLK_BUS_SEL_200M; in rk3568_bus_set_clk()
785 src_clk = ACLK_BUS_SEL_150M; in rk3568_bus_set_clk()
787 src_clk = ACLK_BUS_SEL_100M; in rk3568_bus_set_clk()
789 src_clk = ACLK_BUS_SEL_24M; in rk3568_bus_set_clk()
792 src_clk << ACLK_BUS_SEL_SHIFT); in rk3568_bus_set_clk()
797 src_clk = PCLK_BUS_SEL_100M; in rk3568_bus_set_clk()
799 src_clk = PCLK_BUS_SEL_75M; in rk3568_bus_set_clk()
801 src_clk = PCLK_BUS_SEL_50M; in rk3568_bus_set_clk()
803 src_clk = PCLK_BUS_SEL_24M; in rk3568_bus_set_clk()
806 src_clk << PCLK_BUS_SEL_SHIFT); in rk3568_bus_set_clk()
858 int src_clk; in rk3568_perimid_set_clk() local
863 src_clk = ACLK_PERIMID_SEL_300M; in rk3568_perimid_set_clk()
865 src_clk = ACLK_PERIMID_SEL_200M; in rk3568_perimid_set_clk()
867 src_clk = ACLK_PERIMID_SEL_100M; in rk3568_perimid_set_clk()
869 src_clk = ACLK_PERIMID_SEL_24M; in rk3568_perimid_set_clk()
872 src_clk << ACLK_PERIMID_SEL_SHIFT); in rk3568_perimid_set_clk()
876 src_clk = HCLK_PERIMID_SEL_150M; in rk3568_perimid_set_clk()
878 src_clk = HCLK_PERIMID_SEL_100M; in rk3568_perimid_set_clk()
880 src_clk = HCLK_PERIMID_SEL_75M; in rk3568_perimid_set_clk()
882 src_clk = HCLK_PERIMID_SEL_24M; in rk3568_perimid_set_clk()
885 src_clk << HCLK_PERIMID_SEL_SHIFT); in rk3568_perimid_set_clk()
961 int src_clk; in rk3568_top_set_clk() local
966 src_clk = ACLK_TOP_HIGH_SEL_500M; in rk3568_top_set_clk()
968 src_clk = ACLK_TOP_HIGH_SEL_400M; in rk3568_top_set_clk()
970 src_clk = ACLK_TOP_HIGH_SEL_300M; in rk3568_top_set_clk()
972 src_clk = ACLK_TOP_HIGH_SEL_24M; in rk3568_top_set_clk()
975 src_clk << ACLK_TOP_HIGH_SEL_SHIFT); in rk3568_top_set_clk()
979 src_clk = ACLK_TOP_LOW_SEL_400M; in rk3568_top_set_clk()
981 src_clk = ACLK_TOP_LOW_SEL_300M; in rk3568_top_set_clk()
983 src_clk = ACLK_TOP_LOW_SEL_200M; in rk3568_top_set_clk()
985 src_clk = ACLK_TOP_LOW_SEL_24M; in rk3568_top_set_clk()
988 src_clk << ACLK_TOP_LOW_SEL_SHIFT); in rk3568_top_set_clk()
992 src_clk = HCLK_TOP_SEL_150M; in rk3568_top_set_clk()
994 src_clk = HCLK_TOP_SEL_100M; in rk3568_top_set_clk()
996 src_clk = HCLK_TOP_SEL_75M; in rk3568_top_set_clk()
998 src_clk = HCLK_TOP_SEL_24M; in rk3568_top_set_clk()
1001 src_clk << HCLK_TOP_SEL_SHIFT); in rk3568_top_set_clk()
1005 src_clk = PCLK_TOP_SEL_100M; in rk3568_top_set_clk()
1007 src_clk = PCLK_TOP_SEL_75M; in rk3568_top_set_clk()
1009 src_clk = PCLK_TOP_SEL_50M; in rk3568_top_set_clk()
1011 src_clk = PCLK_TOP_SEL_24M; in rk3568_top_set_clk()
1014 src_clk << PCLK_TOP_SEL_SHIFT); in rk3568_top_set_clk()
1059 int src_clk; in rk3568_i2c_set_clk() local
1062 src_clk = CLK_I2C_SEL_200M; in rk3568_i2c_set_clk()
1064 src_clk = CLK_I2C_SEL_100M; in rk3568_i2c_set_clk()
1066 src_clk = CLK_I2C_SEL_24M; in rk3568_i2c_set_clk()
1075 src_clk << CLK_I2C_SEL_SHIFT); in rk3568_i2c_set_clk()
1124 int src_clk; in rk3568_spi_set_clk() local
1127 src_clk = CLK_SPI_SEL_200M; in rk3568_spi_set_clk()
1129 src_clk = CLK_SPI_SEL_CPLL_100M; in rk3568_spi_set_clk()
1131 src_clk = CLK_SPI_SEL_24M; in rk3568_spi_set_clk()
1137 src_clk << CLK_SPI0_SEL_SHIFT); in rk3568_spi_set_clk()
1142 src_clk << CLK_SPI1_SEL_SHIFT); in rk3568_spi_set_clk()
1147 src_clk << CLK_SPI2_SEL_SHIFT); in rk3568_spi_set_clk()
1152 src_clk << CLK_SPI3_SEL_SHIFT); in rk3568_spi_set_clk()
1198 int src_clk; in rk3568_pwm_set_clk() local
1201 src_clk = CLK_PWM_SEL_100M; in rk3568_pwm_set_clk()
1203 src_clk = CLK_PWM_SEL_24M; in rk3568_pwm_set_clk()
1209 src_clk << CLK_PWM1_SEL_SHIFT); in rk3568_pwm_set_clk()
1214 src_clk << CLK_PWM2_SEL_SHIFT); in rk3568_pwm_set_clk()
1219 src_clk << CLK_PWM3_SEL_SHIFT); in rk3568_pwm_set_clk()
1366 u32 src_clk, mask, shift; in rk3568_crypto_set_rate() local
1374 src_clk = ACLK_SECURE_FLASH_SEL_200M; in rk3568_crypto_set_rate()
1376 src_clk = ACLK_SECURE_FLASH_SEL_150M; in rk3568_crypto_set_rate()
1378 src_clk = ACLK_SECURE_FLASH_SEL_100M; in rk3568_crypto_set_rate()
1380 src_clk = ACLK_SECURE_FLASH_SEL_24M; in rk3568_crypto_set_rate()
1388 src_clk = HCLK_SECURE_FLASH_SEL_150M; in rk3568_crypto_set_rate()
1390 src_clk = HCLK_SECURE_FLASH_SEL_100M; in rk3568_crypto_set_rate()
1392 src_clk = HCLK_SECURE_FLASH_SEL_75M; in rk3568_crypto_set_rate()
1394 src_clk = HCLK_SECURE_FLASH_SEL_24M; in rk3568_crypto_set_rate()
1400 src_clk = CLK_CRYPTO_CORE_SEL_200M; in rk3568_crypto_set_rate()
1402 src_clk = CLK_CRYPTO_CORE_SEL_150M; in rk3568_crypto_set_rate()
1404 src_clk = CLK_CRYPTO_CORE_SEL_100M; in rk3568_crypto_set_rate()
1410 src_clk = CLK_CRYPTO_PKA_SEL_300M; in rk3568_crypto_set_rate()
1412 src_clk = CLK_CRYPTO_PKA_SEL_200M; in rk3568_crypto_set_rate()
1414 src_clk = CLK_CRYPTO_PKA_SEL_100M; in rk3568_crypto_set_rate()
1420 rk_clrsetreg(&cru->clksel_con[27], mask, src_clk << shift); in rk3568_crypto_set_rate()
1470 int src_clk; in rk3568_sdmmc_set_clk() local
1475 src_clk = CLK_SDMMC_SEL_24M; in rk3568_sdmmc_set_clk()
1478 src_clk = CLK_SDMMC_SEL_400M; in rk3568_sdmmc_set_clk()
1481 src_clk = CLK_SDMMC_SEL_300M; in rk3568_sdmmc_set_clk()
1484 src_clk = CLK_SDMMC_SEL_100M; in rk3568_sdmmc_set_clk()
1488 src_clk = CLK_SDMMC_SEL_50M; in rk3568_sdmmc_set_clk()
1492 src_clk = CLK_SDMMC_SEL_750K; in rk3568_sdmmc_set_clk()
1503 src_clk << CLK_SDMMC0_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1508 src_clk << CLK_SDMMC1_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1513 src_clk << CLK_SDMMC2_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1550 int src_clk; in rk3568_sfc_set_clk() local
1554 src_clk = SCLK_SFC_SEL_24M; in rk3568_sfc_set_clk()
1557 src_clk = SCLK_SFC_SEL_50M; in rk3568_sfc_set_clk()
1560 src_clk = SCLK_SFC_SEL_75M; in rk3568_sfc_set_clk()
1563 src_clk = SCLK_SFC_SEL_100M; in rk3568_sfc_set_clk()
1566 src_clk = SCLK_SFC_SEL_125M; in rk3568_sfc_set_clk()
1569 src_clk = SCLK_SFC_SEL_150M; in rk3568_sfc_set_clk()
1577 src_clk << SCLK_SFC_SEL_SHIFT); in rk3568_sfc_set_clk()
1606 int src_clk; in rk3568_nand_set_clk() local
1610 src_clk = NCLK_NANDC_SEL_24M; in rk3568_nand_set_clk()
1613 src_clk = NCLK_NANDC_SEL_100M; in rk3568_nand_set_clk()
1616 src_clk = NCLK_NANDC_SEL_150M; in rk3568_nand_set_clk()
1619 src_clk = NCLK_NANDC_SEL_200M; in rk3568_nand_set_clk()
1627 src_clk << NCLK_NANDC_SEL_SHIFT); in rk3568_nand_set_clk()
1660 int src_clk; in rk3568_emmc_set_clk() local
1664 src_clk = CCLK_EMMC_SEL_24M; in rk3568_emmc_set_clk()
1668 src_clk = CCLK_EMMC_SEL_50M; in rk3568_emmc_set_clk()
1671 src_clk = CCLK_EMMC_SEL_100M; in rk3568_emmc_set_clk()
1674 src_clk = CCLK_EMMC_SEL_150M; in rk3568_emmc_set_clk()
1677 src_clk = CCLK_EMMC_SEL_200M; in rk3568_emmc_set_clk()
1681 src_clk = CCLK_EMMC_SEL_375K; in rk3568_emmc_set_clk()
1689 src_clk << CCLK_EMMC_SEL_SHIFT); in rk3568_emmc_set_clk()
1716 int src_clk; in rk3568_emmc_set_bclk() local
1720 src_clk = BCLK_EMMC_SEL_200M; in rk3568_emmc_set_bclk()
1723 src_clk = BCLK_EMMC_SEL_150M; in rk3568_emmc_set_bclk()
1726 src_clk = BCLK_EMMC_SEL_125M; in rk3568_emmc_set_bclk()
1734 src_clk << BCLK_EMMC_SEL_SHIFT); in rk3568_emmc_set_bclk()
1931 int src_clk; in rk3568_gmac_src_set_clk() local
1935 src_clk = CLK_MAC0_2TOP_SEL_125M; in rk3568_gmac_src_set_clk()
1938 src_clk = CLK_MAC0_2TOP_SEL_50M; in rk3568_gmac_src_set_clk()
1941 src_clk = CLK_MAC0_2TOP_SEL_25M; in rk3568_gmac_src_set_clk()
1949 src_clk << CLK_MAC0_2TOP_SEL_SHIFT); in rk3568_gmac_src_set_clk()
1981 int src_clk; in rk3568_gmac_out_set_clk() local
1985 src_clk = CLK_MAC0_OUT_SEL_125M; in rk3568_gmac_out_set_clk()
1988 src_clk = CLK_MAC0_OUT_SEL_50M; in rk3568_gmac_out_set_clk()
1991 src_clk = CLK_MAC0_OUT_SEL_25M; in rk3568_gmac_out_set_clk()
1994 src_clk = CLK_MAC0_OUT_SEL_24M; in rk3568_gmac_out_set_clk()
2002 src_clk << CLK_MAC0_OUT_SEL_SHIFT); in rk3568_gmac_out_set_clk()
2034 int src_clk; in rk3568_gmac_ptp_ref_set_clk() local
2038 src_clk = CLK_GMAC0_PTP_REF_SEL_62_5M; in rk3568_gmac_ptp_ref_set_clk()
2041 src_clk = CLK_GMAC0_PTP_REF_SEL_100M; in rk3568_gmac_ptp_ref_set_clk()
2044 src_clk = CLK_GMAC0_PTP_REF_SEL_50M; in rk3568_gmac_ptp_ref_set_clk()
2047 src_clk = CLK_GMAC0_PTP_REF_SEL_24M; in rk3568_gmac_ptp_ref_set_clk()
2055 src_clk << CLK_GMAC0_PTP_REF_SEL_SHIFT); in rk3568_gmac_ptp_ref_set_clk()